Portable computing device adapted to update display information while in a low power mode

• US 7,245,945 B2
• Filed: 11/05/2002
• Issued: 07/17/2007
• Est. Priority Date: 11/05/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Paver, Nigel C., Fullerton, Mark
• Primary Examiner(s): Trost; William
• Assistant Examiner(s): DOAN, KIET M
• Application Number:
  US10/289,081
• Publication Number:
  US 20040087351A1
• Time in Patent Office: 1,715 Days
• Field of Search: 455/574, 455/566, 455/552.1, 455/415, 455/556.1, 455/572, 710/13, 370/329, 370/278, 370/342, 713/300, 713/322, 717/146, 345/539
• US Class Current: 455/574
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: H04W 52/0209 in terminal devices terminal devices per se H04W88/02
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Briefly, in accordance with one embodiment of the invention, a portable computing device that has a processor, a direct memory access (DMA) engine, and a display controller may transfer data with the DMA engine to the display. The DMA engine may transfer the data while the processor is in a standby mode and transfer data to the processor while the processor is executing instructions.

Claims

1. A wireless communication device comprising:

a processor having a core region, wherein the processor has at least an operational mode and a standby operational mode;

a direct memory access (DMA) engine; and

a display coupled to the processor, and DMA engine, wherein the wireless communication device is adapted to modify data to be displayed on the display while at least a portion of the core region of the processor is in the standby operational mode, and wherein the DMA engine is adapted to transfer information from a memory to the display while at least a portion of the core region of the processor is in the standby operational mode.

2. The wireless communication device of claim 1, wherein the memory is external to the processor.

3. The wireless communication device of claim 2, wherein the memory is within the processor.

4. The wireless communication device of claim 1, wherein the DMA engine is adapted to transfer information from the memory to a frame buffer in a display controller.

5. The wireless communication device of claim 1, wherein the DMA engine is further adapted to transfer data from a data source to the core of the processor while the processor is in the operational mode.

6. The wireless communication device of claim 5, wherein the data source is an external memory that is external to the processor.

7. The wireless communication device of claim 1, wherein the processor is adapted to halt the execution of instructions while in the standby operational mode.

8. The wireless communication device of claim 1, wherein the data to be displayed is indicative of information selected from the group comprising of current time, received signal strength, transmitted signal strength, and battery life.

9. An apparatus comprising:

a processor, the processor having at least a first operational mode and a second operational mode;

a display controller; and

a direct memory access (DMA) engine to transfer data to the display controller while the processor is in second operational mode, wherein the DMA engine if further adapted to transfer data from a memory to the processor while the processor is in the first operational mode.

10. The apparatus of claim 9, wherein the processor includes a core region and at least a portion of the core region is in an inactive state when the processor in the second operational mode.

11. The apparatus of claim 9, wherein the processor includes a core region and at least a portion of the core region is in an indeterminate logic state when the processor in the second operational mode.

12. The apparatus of claim 9, wherein the processor includes a core region and at least a portion of the core region is provided with a power supply voltage potential when the processor in the second operational mode than when the processor is in the first operational mode.

13. The apparatus of claim 9, wherein the processor does not execute instructions when the processor in the second operational mode.

14. The apparatus of claim 9, where in the memory is external to the processor.

15. A method of displaying information on a display of a portable computing device, comprising:

transferring information from a memory to a display controller with a direct memory access (DMA) engine while a processor in the portable computing device is in a disabled operational mode.

16. The method of claim 15, wherein transferring information includes transferring information upon detection of an event.

17. The method of claim 15, further comprising transferring information to the processor with the DMA engine when the processor is in an enabled operational mode.

18. The method of claim 15, wherein transferring information includes transferring information while the processor has halted the execution of instructions.

19. A method of operating a communication network having a base station and at least one mobile station, the method comprising:

transmitting a signal from the base station to the at least one mobile station so that a processor in the at least one mobile station transitions from a first operational mode to a second operational mode, wherein the processor suspends the execution of instructions and a direct memory access (DMA) engine transfers data from a memory to a display controller while the processor is in the second operation mode.

20. The method of claim 19, further comprising transmitting another signal from the base station to the at least one mobile station so that the processor transitions to the first operation al mode, wherein the DMA engine transfers data to the processor while the processor is in the first operational mode.