Initiation of differential link retraining upon temperature excursion

• US 7,246,022 B2
• Filed: 06/20/2005
• Issued: 07/17/2007
• Est. Priority Date: 06/20/2005
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ruff, Klaus, Shykind, David, McCall, James A.
• Primary Examiner(s): COSIMANO, EDWARD R
• Application Number:
  US11/156,837
• Publication Number:
  US 20060284733A1
• Time in Patent Office: 757 Days
• Field of Search: 324/76.11, 324/105, 374/141, 700/1, 700/71, 700/299, 702/85, 702/99, 702/117, 702/127, 702/130, 702/132, 331/45, 331/70, 331/176, 331/177.R, 331/187, 368/200, 368/201, 368/202
• US Class Current: 702/99
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A method includes detecting a change in temperature in an integrated circuit that is coupled to a differential communication link, and responding to the detected change in temperature by initiating a retraining process for the differential communication link.

Claims

1. A method comprising:

detecting a change in temperature in a first integrated circuit that is coupled to a differential communication link, said differential communication link also coupled to a second integrated circuit to allow exchange of data between the first and second integrated circuits;

responding to said detected change in temperature by initiating a retraining process for said differential communication link; and

performing the initiated retraining process;

wherein the retraining process includes first retraining logic that is part of the first integrated circuit interacting with a first phase interpolator to adjust a phase of a clock signal output from the first phase interpolator, the first phase interpolator being part of the first integrated circuit, the retraining process further including second retraining logic that is part of the second integrated circuit interacting with a second phase interpolator to adjust a phase of a clock signal output from the second phase interpolator, the second phase interpolator being part of the second integrated circuit.

2. The method of claim 1, wherein the second refraining logic initiates said refraining process.

3. The method of claim 1, wherein said detecting includes detecting an output of a thermal diode that is included in said first integrated circuit.

4. The method of claim 1, wherein the first retraining logic initiates said retraining process.

5. The method of claim 4, further comprising:

gating off, during said refraining process, at least some components of said integrated circuit that are not required for said refraining process.

6. A method comprising:

detecting a change of temperature in a first integrated circuit;

sending a signal from said first integrated circuit to a second integrated circuit, said signal to indicate said detected change of temperature, said sending including sending said signal to said second integrated circuit via a differential communication link;

responding to said signal by initiating a refraining process for said differential communication link; and

performing the initiated refraining process;

wherein the refraining process includes first refraining logic that is part of the first integrated circuit interacting with a first phase interpolator to adjust a phase of a clock signal output from the first phase interpolator, the first phase interpolator being part of the first integrated circuit, the retraining process further including second refraining logic that is part of the second integrated circuit interacting with a second phase interpolator to adjust a phase of a clock signal output from the second phase interpolator, the second phase interpolator being part of the second integrated circuit; and

wherein said first integrated circuit is a dynamic random access memory (DRAM) device and said second integrated circuit is a memory controller.