Software controlled content addressable memory in a general purpose execution datapath

• US 7,246,197 B2
• Filed: 01/25/2005
• Issued: 07/17/2007
• Est. Priority Date: 08/27/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bernstein, Debra, Rosenbluth, Mark B., Wolrich, Gilbert
• Primary Examiner(s): Peugh; Brian R.
• Application Number:
  US11/043,782
• Publication Number:
  US 20050132132A1
• Time in Patent Office: 903 Days
• Field of Search: 711/108, 365/49
• US Class Current: 711/108
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A lookup mechanism provides an input value to a datapath element disposed in an execution datapath of a processor and causes the datapath element to compare the input value to stored identifier values. The lookup mechanism receives from the datapath element a result based on the comparison.

Claims

1. A method for use in a processor having multiple multi-threaded programmable engines integrated within the processor:

at a first thread of a one of the multiple multi-threaded engines;

performing a first thread lookup of a tag in a content addressable memory (CAM) within the one of the multiple multi-threaded engines;

if the first thread lookup results in a lookup miss of the tag in the CAM;

initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines into locations in storage internal to the one of the multiple multi-threaded engines;

writing an entry for the tag into the CAM; and

if the first thread lookup results in a lookup hit of the tag in the CAM;

modifying data at at least one of the locations in the storage internal to the one of the multiple multi-threaded engines without initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines;

at a second thread of the one of the multiple multi-threaded engines;

performing a second thread lookup of the tag in a content addressable memory (CAM) within the one of the multiple multi-threaded engines;

if the second thread lookup results in a lookup miss of the tag in the CAM;

initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines into locations in storage internal to the one of the multiple multi-threaded engines;

writing an entry for the tag into the CAM; and

if the second thread lookup results in a lookup hit of the tag in the CAM;

modifying data at at least one of the locations in the storage internal to the one of the multiple multi-threaded engines without initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines.

2. The method of claim 1, further comprising:

writing data at the locations in the storage internal to the one of the multiple multi-threaded engines to the memory external to the one of the multiple multi-threaded engines.

3. The method of claim 1, further comprising determining the locations in the storage for data associated with the tag.

4. The method of claim 3, wherein the determining comprises determining based on an index number of the entry within the CAM.

5. The method of claim 1, further comprising:

at the first thread, locking the entry; and

at the second thread, awaiting unlocking oft the entry before modifying the data.

6. The method of claim 5, wherein the locking comprises writing state data associated with the entry into the CAM.

7. The method of claim 1,

wherein the first thread comprises a thread to process a first packet received from a network;

and

wherein the second thread comprises a thread to process a second packet received from the network.

8. Apparatus including a processor, comprising:

multiple programmable engines integrated within the processor, each of the engines comprising;

registers; and

multiple execution units operationally coupled to the registers to receive input and write output to the registers, the multiple execution units performing operations on operands provided by the registers in response to instructions, the execution units including an arithmetic logic unit (ALU) and a content addressable memory (CAM), at least one of the instructions including at least one opcode bit selecting the CAM among the execution units.

9. The apparatus of claim 8, wherein the multiple programmable engines comprise multiple multi-threaded programmable engines, wherein each of the engines includes multiple program counters for each respective thread provided by the engines.

10. The apparatus of claim 9, wherein the ALU and the CAM are configured in parallel with respect to the registers.

11. The apparatus of claim 9, wherein:

if a CAM entry matches a tag being looked up, the CAM is configured to output a hit signal; and

if no CAM entry matches a tag being lookup up, the CAM is configured to output a miss signal and a number of the least recently used CAM entry.

12. The apparatus of claim 9, wherein the registers comprise a register file.

13. The apparatus of claim 9, wherein the registers comprise registers that buffer data transferred to memory external to an engine and registers that buffer data being transferred directly between engines.

14. The apparatus of claim 9, wherein the instructions comprise a CAM lookup instruction and a CAM write instruction.

15. A system, comprising:

at least one Ethernet media access controller,

at least one processor coupled to the at least one Ethernet media access controller, the processor comprising;

multiple multi-threaded programmable engines integrated within the processor, multiple ones of the engines comprising;

registers;

multiple execution units operationally coupled to the registers to receive input and write output to the registers, the multiple execution units performing operations on operands provided by the registers in response to instructions, the execution units including an arithmetic logic unit (ALU) and a content addressable memory (CAM), at least one of the instructions including at least one bit selecting the CAM among the execution units.

16. The system of claim 15,

wherein the ALU and the CAM are configured in parallel with respect to the registers;

where in;

if a CAM entry matches a tag being looked up, the CAM is configured to output a hit signal; and

if a CAM entry does riot match a tag being lookup up, the CAM is configured to output a miss signal and output a number of the least recently used CAM entry; and

wherein the instructions comprise a CAM lookup instruction and a CAM write instruction.

17. A computer program product residing on a computer-readable medium comprising instructions to cause a computer, including a processor having multiple multi-threaded programmable engines integrated within the processor, to perform operations comprising:

at a first thread of a one of the multiple multi-threaded engines;

performing a first thread lookup of a tag in a content addressable memory (CAM) within the one of the multiple multi-threaded engines;

if the first thread lookup results in a lookup miss of the tag in the CAM;

initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines into locations in storage internal to the one of the multiple multi-threaded engines;

writing an entry for the tag into the CAM; and

if the first thread lookup results in a lookup hit of the tag in the CAM;

modifying data at at least one of the locations in the storage internal to the one or the multiple multi-threaded engines without initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines;

at a second thread of the one of the multiple multi-threaded engines;

performing a second thread lookup of the tag in a content addressable memory (CAM) within the one of the multiple multi-threaded engines;

if the second thread lookup results in a lookup miss of the tag in the CAM;

initiating a read of data associated with the tag from memory external to the one of the multiple multi-threaded engines into locations in Storage internal to the one of the multiple multi-threaded engines;

writing an entry for the tag into the CAM; and

if the second thread lookup results in a lookup hit of the tag in the CAM;

modifying data at at least one of the locations in the storage internal to the one of the multiple multi-threaded engines without initiating at read of data associated with the tag from memory external to the one of the multiple multi-threaded engines.

18. The computer program product of claim 17,

wherein the first thread comprises a thread to process a first packet received from a network;

and

wherein the second thread comprises a thread to process a second packet received from the network.