Systolic memory arrays

• US 7,246,215 B2
• Filed: 11/26/2003
• Issued: 07/17/2007
• Est. Priority Date: 11/26/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ye, Yibin, Lu, Shih-Lien L., Somasekhar, Dinesh
• Primary Examiner(s): Elmore; Stephen C.
• Assistant Examiner(s): KIM, DANIEL Y
• Application Number:
  US10/721,178
• Publication Number:
  US 20050114618A1
• Time in Patent Office: 1,329 Days
• Field of Search: 370/503, 711/169, 711/100, 711/101, 711/167, 711/170, 710/3, 710/36, 710/38, 365/189.01, 365/230.03
• US Class Current: 711/169
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G06F 2212/271 Non-uniform cache access [NUCA] architecture
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency and faster performance is achieved with this memory, because each bank is smaller in size and is accessed more rapidly. A high throughput rate is accomplished because of the pipelining. Memory is accessed at the pipeline frequency with the proposed read and write mechanism. Design complexity is reduced because each bank within the memory is the same and repeated. The memory array size is re-configured and organized to fit within desired size and area parameters.

Claims

1. A memory comprising:

a plurality of systolic memory arrays each divided into banks, each of the memory arrays arranged in a pipelined architecture and each of the plurality of systolic memory arrays to support pipeline access to the corresponding banks using a plurality of data pipes; and

a plurality of pipeline registers, each register to couple to a first one of the banks of a corresponding one of the plurality of systolic memory arrays to provide read and write operations through a data pipe to the banks of the corresponding one of the systolic memory arrays beginning with the first one of the banks and to provide address access through an address pipe to the banks of the corresponding one of the systolic memory arrays beginning with the first one of the banks.

2. The memory of claim 1, wherein at least one of the plurality of data pipes is used for a reading operation.

3. The memory of claim 1, wherein at least one of the plurality of data pipes is used for a writing operation.

4. The memory of claim 1, each of the plurality of systolic memory arrays includes at least eight banks.

5. The memory of claim 1, wherein a number of pipeline stages used depends upon an access latency of each bank and a desired throughput rate.

6. The memory of claim 1, wherein a clock frequency and a data path width for the pipeline architecture is determined.

7. The memory of claim 1, wherein a number of pipeline stages relates to a number of clock cycles.

8. The memory of claim 7, wherein the number of pipeline stages is the same as the number of clock cycles.

9. The memory of claim 1, wherein each of the plurality of systolic memory arrays is divided into a horizontal arrangement.

10. The memory of claim 1, wherein each of the plurality of systolic memory arrays is divided into a vertical arrangement.

12. The memory of claim 1, wherein a read operation from the memory is performed by pumping an address once and allowing the address to flow through the address pipe to reach individual banks of one of the systolic memory arrays one cycle at a time.

13. The memory of claim 1, wherein memory operations from different banks having different memory addresses of one of the systolic memory arrays are interleaved.

15. The memory of claim 1, wherein whenever a bank receives a read address, memory access is initiated.

16. The memory of claim 1, wherein access latency for a bank is represented by 2i+L, where i represents the time it takes to allow an address to reach a desired i th bank and L represents the-cycles of latency to access the memory.

17. The memory of claim 16, wherein it will take i cycles to allow data to come out of the i th bank through a read pipeline.

18. The memory of claim 16, wherein to avoid memory collisions among data, a second read access of consecutive reads delays the-placement of read result on the read data pipeline by a specified idle time.

19. The memory of claim 18, wherein the specified idle time is at least one clock cycle.

23. The memory of claim 1, wherein each bank is associated with a mechanism to support addressing each data operations of the corresponding bank.

11. A memory comprising:

a plurality of systolic memory arrays each divided into banks, each of the systolic memory arrays arranged in a pipelined architecture and each of the plurality of memory arrays to support pipeline access to the corresponding banks using a plurality of data pipes, and a writing operation into the memory is performed by pumping an address with data that is to be written into the memory; and

a plurality of pipeline registers, each register to couple to a first one of the banks of a corresponding one of the plurality of systolic memory arrays through a data pipe and an address pipe to provide read/write data input, data output and address access to the banks of the corresponding one of the systolic memory arrays through the first one of the banks arranged in the pipelined architecture.

14. The memory of claim 11, wherein peripheral access for one systolic memory array is accomplished from one side of the one systolic memory array.

20. A processing system comprising:

a die including a microprocessor;

peripheral equipment coupled to the processing system;

a network interface; and

on-die or off-die systolic memory including;

a plurality of separate systolic memory arrays, each systolic memory array including a plurality of memory banks in a pipelined fashion, the plurality of memory banks of each systolic memory array to share an address line in a pipelined fashion and data lines in a pipelined fashion, and a read operation from the systolic memory is performed by pumping an address once and allowing the address to flow through an address pipe to reach individual banks one cycle at a time, and

a plurality of pipeline registers. each register coupled to one of the separate systolic memory arrays, and each register is coupled to one end of a corresponding one of the systolic memory arrays to provide read data from the memory array, to provide write data to the array and to provide address information to the array.

21. The processing system of claim 20, wherein each bank is associated with a mechanism to support addressing and data operations.

22. The processing system of claim 20, wherein access latency for a bank is represented by 2i+L, where i represents the time it takes to allow an address to reach a desired i th bank and L represents the-cycles of latency to access the memory.

24. A memory comprising:

a plurality of separate systolic memory arrays, each systolic memory array including a plurality of memory banks in pipelined fashion, the plurality of memory banks of each memory array to share an address line in a pipelined fashion and data lines in a pipelined fashion, and a read operation is performed by pumping an address and allowing the address to flow through the address line to reach individual banks of one of the plurality of separate systolic memory arrays one cycle at a time, and access latency for one bank of one of the plurality of senarate systolic memory arrays is represented by 2i+L, where i represents time it takes to allow an address to reach a desired i th bank and L represents cycles of latency to access the memory.

25. The memory of claim 24, further comprising:

a plurality of pipeline registers, each register to couple to one of the separate systolic memory arrays.

26. The memory of claim 24, wherein each bank is associated with a mechanism to support addressing and data operations.

27. A memory comprising:

a plurality of separate systolic memory arrays, each systolic memory array including a plurality of memory banks in pipelined fashion, the plurality of memory banks of each systolic memory array to share an address line in a pipelined fashion and data lines in a pipelined fashion, and peripheral access for writing operations and addressing for one systolic memory array is accomplished from one side of the one systolic memory array and data for reading operations for the one systolic memory array is received from the one side of the one systolic memory array.