Method and apparatus for dynamic degradation detection

• US 7,246,268 B2
• Filed: 01/16/2002
• Issued: 07/17/2007
• Est. Priority Date: 01/16/2002
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mangan, John S., Craig, Jeffrey
• Primary Examiner(s): Baderman; Scott
• Assistant Examiner(s): CONTINO, PAUL F
• Application Number:
  US10/051,833
• Publication Number:
  US 20030135793A1
• Time in Patent Office: 2,008 Days
• Field of Search: 714/42, 714/7, 714/8, 714/54, 714/57, 714/710, 714/711
• US Class Current: 714/42
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

Methods and apparatus for automatically detecting when a memory system has significantly degraded are disclosed. According to one aspect of the present invention, a method for determining a status associated with a memory system which includes a plurality of sectors includes updating a counter, comparing the counter to a threshold value, and generating an appropriate indication when comparing the counter to the threshold value yields a first result. The counter is updated each time a sector is reassigned, and indicates a number of sectors remaining in the memory system. The threshold value indicates a number of sectors which are yet to be reassigned in order for the memory system to be considered as useable, or reliable. The indication is generated when comparing the counter to the threshold value yields a first result to indicate that the memory system is substantially near a failure condition.

Claims

1. A memory system for storing information, the memory system comprising:

a first plurality of spare units of erase on a first chip;

a second plurality of spare units of erase on a second chip;

a first storage element on the first chip, the first storage element containing a first counter and a first threshold, the first counter indicating a number of spare units of erase on the first chip which have not yet been reassigned;

a second storage element on the second chip;

the second storage element containing a second counter and a second threshold, the second counter indicating a number of spare units of erase on the second chip which have not yet been reassigned;

a controller, the controller updating the first counter each time a spare unit of erase of the first plurality of spare units of erase is reassigned, the controller comparing the first counter to the first threshold value, the controller updating the second counter each time a spare unit of erase of the second plurality of spare units of erase is reassigned, the controller comparing the second counter to the second threshold value, the controller generating an end-of-life indicator when either the first counter reaches the first threshold or the second counter reaches the second threshold; and

wherein the memory system operates in conjunction with a host system and the controller reassigns a spare unit of erase in response to a request from the host system.

2. The memory system of claim 1 wherein when the controller compares the first counter to the first threshold value to determine if the memory system is in an end-of-life the condition, the controller determines that the memory system is in the end-of-life condition when a value of the first counter is less than or equal to the first threshold value.

3. The memory system of claim 1 wherein the controller attempts to write data to a first unit of erase on the first chip, and determines if the first unit of erase is worn.

4. The memory system of claim 3 wherein when it is determined that the first unit of erase is worn, the controller reassigns a first spare unit of erase included in the first plurality of spare units of erase as the first unit of erase.

5. The memory system of claim 4 wherein the controller writes the data into the reassigned first spare unit of erase.

6. The memory system of claim 1 wherein the controller attempts to write data to a first unit of erase on the first chip to determine if the first unit of erase is defective.

7. The memory system of claim 6 wherein when it is determined that the first unit of erase is defective, the controller reassigns a first spare unit of erase included in the first plurality of spare units of erase as the first unit of erase.

8. The memory system of claim 7 wherein the controller writes the data into the reassigned first spare unit of erase.

9. The memory system of claim 1 wherein an individual one of the first plurality of spare units of erase is a sector, and an individual one of the second plurality of spare units of erase is a spare sector.

10. The memory system of claim 1 further including:

a non-volatile memory, wherein the first plurality of spare units of erase, the second plurality of spare units of erase, and the first storage element are included in the non-volatile memory.

11. The memory system of claim 1 wherein the memory system is a non-volatile memory system.

12. The memory system of claim 1 wherein the memory system is one of a PC card, a CompactFlash card, a MultiMedia card, a MemoryStick card, and a Secure Digital card.

13. The system of claim 1 wherein the host system is arranged to capture information and to attempt to store the information in the memory system.

14. The system of claim 13 wherein the information is one of audio information and wireless information.

15. The system of claim 14 wherein the host system is one of a cellular communications device, and audio player, and a video player.