Efficient memory check architecture and method
First Claim
Patent Images
1. A method of testing a memory coupled to a processing node comprising the steps of:
- initializing, responsive to the processing node executing a basic input/output system (BIOS) program, a background scrubber in the processing node to perform a test of the memory;
checking a status of said background scrubber in which said status indicates whether an error occurred during said test; and
taking a predetermined action in response to said status indicating that said error occurred during said test.
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Abstract
Methods and apparatus are provided for use in testing a memory (230) coupled to a processing node (214). A background scrubber (316) in the processing node (214) is initialized to perform a test of the memory (230). A status of the background scrubber (316) is checked in which the status indicates whether an error occurred during the test. A predetermined action is taken in response to the status indicating that the error occurred during the test.
55 Citations
31 Claims
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1. A method of testing a memory coupled to a processing node comprising the steps of:
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initializing, responsive to the processing node executing a basic input/output system (BIOS) program, a background scrubber in the processing node to perform a test of the memory; checking a status of said background scrubber in which said status indicates whether an error occurred during said test; and taking a predetermined action in response to said status indicating that said error occurred during said test. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. In a multiprocessing system having a plurality of processing nodes each including a memory, a method comprising the steps of:
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initializing, responsive to one of the plurality of processor nodes executing a basic input/output system (BIOS) program, a background scrubber in each of the plurality of processing nodes to perform a test of the memory; checking a status of said background scrubber in each of the plurality of processing nodes in which said status indicates whether an error occurred during said test of the memory; and taking a predetermined corrective action in each of the plurality of processing nodes in which said status indicates that at least one error occurred during said test of the memory. - View Dependent Claims (12, 13, 14)
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15. A method of testing a memory coupled to a processing node comprising the steps of:
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performing a test of a plurality of locations in the memory using a background scrubber, responsive to the processing node executing a basic input/output system (BIOS) program that initializes the background scrubber; determining whether an error occurred during said test; taking a predetermined corrective action in response to at least one non-correctable error; and taking a different action in response to at least one correctable error. - View Dependent Claims (16, 17, 18)
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19. A basic input/output system (BIOS) memory adapted to be coupled to a boot strap processor (BSP) comprising:
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a first set of instructions executable by said BSP to initialize a background scrubber in a processor node to test a predetermined portion of a memory; a second set of instructions executable by said BSP to determine when said background scrubber has tested said predetermined portion of said memory; a third set of instructions executable by said BSP to determine whether any errors occurred when said background scrubber tested said predetermined portion of said memory; and a fourth set of instructions executable by said BSP to take a predetermined corrective action in response to said third set of instructions determining that at least one error occurred. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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27. In a computer system having a memory, a method comprising the steps of:
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testing a plurality of locations of the memory using a background scrubber, responsive to a processing node executing a basic input/output system (BIOS) program that initializes the background scrubber; determining whether an error occurred during said step of testing; if said error occurred determining whether said error is correctable or non-correctable; if said error occurred and is non-correctable, reconfiguring the memory to exclude a memory location; and taking a predetermined action if said error occurred and is correctable. - View Dependent Claims (28, 29, 30, 31)
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Specification