Method and apparatus for estimating random jitter (RJ) and deterministic jitter (DJ) from bit error rate (BER)

• US 7,246,274 B2
• Filed: 09/10/2004
• Issued: 07/17/2007
• Est. Priority Date: 09/10/2004
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Kizer, Jade M., Madden, Christopher J.
• Primary Examiner(s): Chase; Shelly
• Application Number:
  US10/939,028
• Publication Number:
  US 20060059392A1
• Time in Patent Office: 1,040 Days
• Field of Search: 714/704
• US Class Current: 714/704
• CPC Class Codes: G01R 31/31709 Jitter measurements; Jitter generators measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901
• CPC Class Codes: G01R 31/3171 BER [Bit Error Rate] test
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G11C 29/022 in I/O circuitry

Abstract

An apparatus and method provides prediction of BER for an interface between ICs, such as a processor and a memory device, without using special test equipment. A known data pattern or PRBS is transmitted to a receiver, which compares the received data values with expected data values to determine if a bit error has occurred in an embodiment of the present invention. A center of data eye and the edge of the data eye are sampled (over sampled) in order to determine if a bit error has occurred in an alternate embodiment of the present invention. A first counter is used to count the total number of bits sampled and the second counter is used to count the number of errors that occurred in the total number of bits sampled.

Claims

1. A method, comprising:

obtaining a plurality of error rates corresponding to a plurality of sampling clock offset values;

transforming the plurality of error rates to obtain a plurality of transformed error rates;

forming a linear relationship between the plurality of transformed error rates and the plurality of sampling clock offset values;

obtaining a deterministic jitter value from the linear relationship; and

obtaining a random jitter value from the linear relationship.

2. The method of claim 1, further comprising:

transmitting, by a transmitter, a predetermined sequence of data values.

3. The method of claim 2, further comprising receiving a plurality of data values, wherein a receiver samples the plurality of data values with the plurality of sampling clock offset values.

4. The method of claim 1, wherein a master device performs the obtaining and transforming.

5. The method of claim 1, further comprising counting a number of data values by a logarithmic counter.

6. The method of claim 1, further comprising counting a number of data values by an overflow protected counter.

7. The method of claim 1, further comprising:

counting a number of errors by comparing a plurality of expected data values to a plurality of measured data values.

8. The method of claim 1, further comprising:

counting a number of errors by oversampling a plurality of data values.

9. The method of claim 1, wherein the transforming includes performing an inverse standard normal cumulative distribution function.

10. The method of claim 1, wherein the forming includes performing a linear fit on the plurality of transformed error rates and the plurality of sampling clock offset values.

11. The method of claim 10, wherein the plurality of transformed error rates are plotted versus the plurality of sampling clock offset values.

12. The method of claim 1, wherein the obtaining the deterministic jitter value is obtained from a difference between a first x-intercept of a first line and a second x-intercept of a second line formed by plotting the plurality of transformed error rates versus the plurality of sampling clock offset values.

13. The method of claim 1, further comprising:

using the deterministic jitter value and random jitter value in a Fibre Channel jitter model equation.

14. The method of claim 1, wherein a memory device and a master device performs the method.

15. A method, comprising:

adjusting a sampling signal by a first plurality of offset values;

counting a plurality of data values to obtain a total number of data values for respective offset values in the first plurality of offset values;

counting a number of errors in the plurality of data values for respective offset values in the first plurality of offset values;

calculating a first plurality of error rates in response to the total number of data values in the plurality of data values and the number of errors in the plurality of data values for respective offset values in the first plurality of offset values;

adjusting the sampling signal by a second plurality of offset values;

counting a plurality of data values to obtain a total number of data values for respective offset values in the second plurality of offset values;

counting a number of errors in the plurality of data values for respective offset values in the second plurality of offset values;

calculating a second plurality of error rates in response to the total number of data values in the plurality of data values and the number of errors in the plurality of data values for respective offset values in the second plurality of offset values;

transforming the first and second plurality of error rates to obtain a first and second plurality of transformed error rates;

forming a first and second linear relationship between the first and second plurality of transformed error rates and the first and second plurality of offset values, respectively;

obtaining a deterministic jitter value from the first and second linear relationship; and

obtaining a random jitter value from the first and second linear relationship.

16. The method of claim 15, further comprising:

transmitting a predetermined sequence of data values.

17. The method of claim 15, wherein a transmitter performs the adjusting.

18. The method of claim 15, wherein a receiver performs the adjusting.

19. The method of claim 15, wherein a logarithmic counter performs the counting.

20. The method of claim 15, wherein a counter having overflow protection performs the counting.

21. The method of claim 15, wherein the counting the number of errors includes comparing expected data values to measured data values.

22. The method of claim 15, wherein the counting the number of errors includes oversampling a data value in the plurality of data values.

23. The method of claim 15, wherein the transforming includes performing an inverse standard normal cumulative distribution function.

24. The method of claim 15, wherein the forming includes performing a first and second linear fit on the first and second plurality of transformed error rates and the first and second plurality of offset values.

25. The method of claim 24, wherein the first and second plurality of transformed error rates are plotted versus the first and second plurality of offset values.

26. The method of claim 15, wherein the obtaining the deterministic jitter value is obtained from a difference between a first x-intercept of a first line and a second x-intercept of a second line formed by plotting the first and second plurality of transformed error rates versus the first and second plurality of offset values, respectively.

27. The method of claim 15, wherein the obtaining the random jitter value is obtained from an inverse of a magnitude of a slope of a line formed by plotting the first plurality of transformed error rates versus the first plurality of offset values.

28. The method of claim 15, further comprising:

using the deterministic jitter value and random jitter value in a Fibre Channel jitter model equation.

29. The method of claim 15, wherein a memory device and a master device performs the method.

30. An apparatus, comprising:

a receiver to sample a plurality of data values in response to a plurality of sampling clock offset values;

wherein the receiver includes;

a first counter to indicate a number of data values received by the receiver,

a second counter to indicate a number of errors in the number of data values, and

a processing device, coupled to the receiver;

wherein the processing device;

obtains a plurality of error rates corresponding to the plurality of sampling clock offset values, wherein a first error rate in the plurality of error rates is calculated in response to the number of data values and the number of errors,

transforms the plurality of error rates to obtain a plurality of transformed error rates,

forms a linear relationship between the plurality of transformed error rates and the plurality of sampling clock offset values,

obtains a deterministic jitter value from the linear relationship, and

obtains a random jitter value from the linear relationship.

31. The apparatus of claim 30, further comprising a transmitter to transmit a predetermined sequence of data values.

32. The apparatus of claim 30, wherein the first counter is a logarithmic counter.

33. The apparatus of claim 30, wherein the first counter is an overflow protected counter.

34. The apparatus of claim 30, wherein the receiver includes:

a pattern checker to compare the plurality of received data values to a plurality of expected data values.

35. The apparatus of claim 30, wherein the receiver includes:

a sampler to oversample the plurality of data values.

36. The apparatus of claim 30, wherein the transforms includes a calculation of inverse standard normal cumulative distribution function.

37. The apparatus of claim 30, wherein the forms includes a linear fit on the plurality of transformed error rates and the plurality of sampling clock offset values.

38. The apparatus of claim 37, wherein the plurality of transformed error rates are plotted versus the plurality of sampling clock offset values.

39. The apparatus of claim 30, wherein the deterministic jitter value is obtained from a difference between a first x-intercept of a first line and a second x-intercept of a second line formed by plotting the plurality of transformed error rates versus the plurality of sampling clock offset values.

40. The apparatus of claim 30, wherein the random jitter value is obtained from an inverse of a magnitude of a slope of a line formed by plotting the plurality of transformed error rates versus the plurality sampling clock offset values.

41. The apparatus of claim 30, wherein the deterministic jitter value and random jitter value is used in a Fibre Channel jitter model equation.

42. An apparatus, comprising:

an integrated circuit that operates in a first and second mode of operation,

wherein the first mode of operation a receiver samples a plurality of data values in response to a first plurality of sampling clock offset values,

wherein the second mode of operation a transmitter generates a plurality of data values in response to a second plurality of sampling clock offset values,

a first counter to indicate a number of data values received by the receiver,

a second counter to indicate a number of errors in the number of data values, and

a processing device, coupled to the integrated circuit;

wherein the processing device;

obtains a plurality of error rates corresponding to either the first or second plurality of sampling clock offset values, wherein a first error rate in the plurality of error rates is calculated in response to the number of data values and the number of errors,

transforms the plurality of error rates to obtain a plurality of transformed error rates,

forms a linear relationship between the plurality of transformed error rates and either the first or second plurality of sampling clock offset values,

obtains a deterministic jitter value from the linear relationship, and

obtains a random jitter value from the linear relationship.

43. An apparatus, comprising:

an integrated circuit memory device including,

a transmitter to generate a plurality of data values,

a receiver to receive the plurality of data values,

a first counter to indicate a number of data values received by the receiver,

a second counter to indicate a number of errors in the number of data values, and

a processing device, coupled to the integrated circuit memory device;

wherein the processing device;

obtains a plurality of error rates corresponding to a plurality of sampling clock offset values, wherein a first error rate in the plurality of error rates is calculated in response to the number of data values and the number of errors,

transforms the plurality of error rates to obtain a plurality of transformed error rates,

forms a linear relationship between the plurality of transformed error rates and the plurality of sampling clock offset values,

obtains a deterministic jitter value from the linear relationship, and

obtains a random jitter value from the linear relationship.

44. An apparatus, comprising:

a receiver to receive a plurality of data values in response to a sample clock signal; and

,

means, coupled to the receiver, for providing a deterministic jitter value and a random jitter value based on a linear relationship between a plurality of bit error rates and corresponding sample clock offset values.

45. An apparatus, comprising:

a receiver capable to receive a plurality of data values in response to a sample clock signal; and

,

means, coupled to the receiver, for calculating a plurality of bit error rate values corresponding to a plurality of sample clock offset in either the transmitter or receiver, or both.