Analyzing substrate noise
First Claim
1. A system for analyzing substrate noise (SN), the system comprising:
- a static timing analysis (STA) module operable to apply an STA algorithm to a description of a digital circuit, application of the STA algorithm generating timing information on one or more gates in the digital circuit;
a current waveform generator operable to apply a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit, application of the CWG algorithm generating a current waveform; and
a reduced model (RM) generator operable to generate an RM of the digital circuit for simulation, the RM generator generating the RM of the digital circuit according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit, simulation of the RM of the digital circuit generating an indication of noise in a substrate associated with the digital circuit.
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Accused Products
Abstract
In one embodiment, a method for analyzing substrate noise includes applying a static timing analysis (STA) algorithm to a description of a digital circuit. Application of the STA algorithm generates timing information on one or more gates in the digital circuit. The method also includes applying a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit. Application of the CWG algorithm generates a current waveform. The method also includes generating a reduced model (RM) of the digital circuit for simulation according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit. Simulation of the RM of the digital circuit generates an indication of noise in a substrate associated with the digital circuit.
19 Citations
34 Claims
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1. A system for analyzing substrate noise (SN), the system comprising:
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a static timing analysis (STA) module operable to apply an STA algorithm to a description of a digital circuit, application of the STA algorithm generating timing information on one or more gates in the digital circuit; a current waveform generator operable to apply a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit, application of the CWG algorithm generating a current waveform; and a reduced model (RM) generator operable to generate an RM of the digital circuit for simulation, the RM generator generating the RM of the digital circuit according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit, simulation of the RM of the digital circuit generating an indication of noise in a substrate associated with the digital circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for analyzing substrate noise (SN), the method comprising:
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applying a static timing analysis (STA) algorithm to a description of a digital circuit, application of the STA algorithm generating timing information on one or more gates in the digital circuit; applying a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit, application of the CWG algorithm generating a current waveform; and generating a reduced model (RM) of the digital circuit for simulation according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit, simulation of the RM of the digital circuit generating an indication of noise in a substrate associated with the digital circuit. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. Software for analyzing substrate noise (SN), the software encoded in a computer-readable medium and when executed operable to:
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apply a static timing analysis (STA) algorithm to a description of a digital circuit, application of the STA algorithm generating timing information on one or more gates in the digital circuit; apply a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit, application of the CWG algorithm generating a current waveform; and generate a reduced model (RM) of the digital circuit for simulation according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit, simulation of the RM of the digital circuit generating an indication of noise in a substrate associated with the digital circuit. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A system for analyzing substrate noise (SN), the system comprising:
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means for applying a static timing analysis (STA) algorithm to a description of a digital circuit, application of the STA algorithm generating timing information on one or more gates in the digital circuit; means for applying a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit, application of the CWG algorithm generating a current waveform; and means for generating a reduced model (RM) of the digital circuit for simulation according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit, simulation of the RM of the digital circuit generating an indication of noise in a substrate associated with the digital circuit.
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Specification