Plasma density, energy and etch rate measurements at bias power input and real time feedback control of plasma source and bias power

• US 7,247,218 B2
• Filed: 05/16/2003
• Issued: 07/24/2007
• Est. Priority Date: 05/16/2003
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Hoffman, Daniel J.
• Primary Examiner(s): Hassanzadeh; Parviz
• Assistant Examiner(s): GRAMAGLIA, MAUREEN
• Application Number:
  US10/440,364
• Publication Number:
  US 20040226657A1
• Time in Patent Office: 1,530 Days
• Field of Search: 156/345.24, 156/345.25, 156/345.28, 156/345.43, 156/345.44, 156/345.47, 118/697, 118/712, 118/715, 118/723, 118/723.E, 315/111.21, 216/59, 216/61, 216/67
• US Class Current: 156/345.28
• CPC Class Codes: H01J 37/32174 Circuits specially adapted for controlling the RF discharge
• CPC Class Codes: H01J 37/32935 Monitoring and controlling tubes by information coming from the object and/or discharge

Abstract

A plasma reactor process measurement instrument includes an input phase processor receiving wafer bias voltage, current and power and computing an input impedance, an input current and an input voltage to the transmission line; a transmission line processor for computing a junction admittance of a junction between the transmission line and the conductive grid from the input impedance, input current and input voltage and from parameters of the transmission line; a grid-to-ground transformation unit for providing shunt electrical quantities of a shunt capacitance between the grid and a ground plane; a grid-to-wafer transformation unit for providing load electrical quantities of a load capacitance between the grid and the wafer; and, a combined transformation processor for computing the at least one of the etch rate, plasma ion density and wafer voltage from the junction admittance, the shunt electrical quantities, the load electrical quantities and a frequency of the RF power generator.

Claims

1. A plasma reactor having an instrument for measuring at least one of:

(a) etch rate, (b) plasma ion density, (c) wafer voltage, during processing of a semiconductor wafer on a workpiece support within a chamber of the plasma reactor containing a plasma, said reactor including an RF power generator coupled from an impedance match circuit through a transmission line to a conductive grid within the workpiece support, said impedance match circuit including sensing circuitry, said instrument comprising;

an input phase processor connected to said sensing circuitry and configured to compute from outputs of said sensing circuitry an input impedance, an input current and an input voltage to said transmission line;

a transmission line processor configured to compute a junction admittance of a junction between said transmission line and said conductive grid from said input impedance, input current and input voltage and from parameters of said transmission line;

a grid-to-ground transformation unit configured to provide shunt electrical quantities of a shunt capacitance between said grid and a ground plane;

a grid-to-wafer transformation unit configured to provide load electrical quantities of a load capacitance between said grid and said wafer; and

a combined transformation processor configured to compute the at least one of said etch rate, plasma ion density and wafer voltage from all of the following;

said junction admittance, said shunt electrical quantities, said load electrical quantities and a frequency of said RF power generator.

2. The reactor of claim 1 wherein said instrument is further for measuring wafer current, and wherein said combined transformation processor further is configured to compute said wafer current from said junction admittance, said shunt electrical quantities and said load electrical quantities.

3. The reactor of claim 1 wherein said input phase processor, said transmission line processor, said grid-to-ground transformation unit, said grid-to-wafer transformation unit and said combined transformation processor comprise shared resources within a common microprocessor.

4. The reactor of claim 1 wherein said parameters of said transmission line processor comprise a length of said transmission line, a characteristic impedance of said transmission line and a complex loss factor of said transmission line.

5. The reactor of claim 1 wherein said grid-to-ground transformation unit is configured to compute said shunt electrical quantities from the size of a grid-to-ground gap length, an area of said wafer, a grid-to-ground dielectric constant and a grid-to-ground conductive loss component.

6. The reactor of claim 1 wherein said grid-to-ground transformation unit comprises a memory storing said shunt electrical quantities.

7. The reactor of claim 1 wherein said grid-to-wafer transformation unit is configured to compute said load electrical quantities from a grid-to-wafer gap length, an area of said wafer, a grid-to-wafer dielectric constant and a grid-to-wafer conductive loss component.

8. The reactor of claim 1 wherein said grid-to-wafer transformation unit comprises a memory storing said load electrical quantities.

9. The reactor of claim 1 wherein said combined transformation processor is configured to compute said wafer voltage and an imaginary part of a plasma admittance comprising a plasma susceptance, and is configured to compute at least one of said ion density and etch rate from said wafer voltage and said plasma susceptance.

10. The reactor of claim 1 further comprising a bias power feedback controller comprising:

(a) a circuit configured to furnish a wafer voltage target value,

(b) a subtractor configured to compute a wafer voltage error between said wafer voltage measurement signal and said wafer voltage target value, and

(c) a circuit configured to generate a bias power control signal from said wafer voltage error and configured to apply said bias power control signal to said plasma RF bias power supply so as to govern the output power of said plasma RF bias power supply in a manner that tends to reduce said wafer voltage error.

11. The plasma reactor of claim 10 wherein said circuit configured to generate a bias power control signal comprises:

a circuit configured to generate a bias power feedback gain factor; and

a multiplier configured to multiply said wafer voltage error by said bias power feedback gain factor to produce said bias power control signal.

12. The plasma reactor of claim 10 wherein said circuit furnishing a wafer voltage target value comprises a memory containing said wafer voltage target value.

13. The plasma reactor of claim 10 wherein said measurement instrument converts said voltage and current measurement signals into an ion density measurement signal representing plasma ion density in said chamber, said plasma reactor further comprising a source power feedback controller, said source power feedback controller comprising:

(a) a circuit configured to furnish an ion density target value,

(b) a subtractor configured to compute an ion density error between said ion density measurement signal and said ion density target value, and

(c) a circuit configured to generate a source power control signal from said ion density error and configured to apply said source power control signal to said plasma RF source power supply so as to govern the output power of said plasma RF source power supply in a manner that tends to reduce said ion density error.

14. The reactor of claim 13 further comprising:

a memory storing sets of contours of constant performance parameter values for one of bias power and source power as a function of the other, said sets of contours comprising at least two of a set of contours of constant wafer voltage, a set of contours of constant ion density, and a set of contours of constant etch rate;

a process set point controller configured to accept user-defined target values for control parameters comprising at least two of wafer voltage, ion density and etch rate corresponding to the set of contours stored in said memory, and configured to find a pair of source power and bias power values at which the corresponding ones of said contours of constant performance parameter values intersect; and

said process set point controller having an output at which said pair of source power and bias power values are coupled as power level commands to said plasma RF source power supply and said plasma RF bias power supply, respectively.

15. The plasma reactor of claim 14 wherein said sets of contours comprise different sets of said contours for different chamber pressures.

16. The plasma reactor of claim 14 wherein said sets of contours comprise different sets of contours for different values of a control parameter.

17. The plasma reactor of claim 1 wherein said measurement instrument converts said voltage and current measurement signals into an ion density measurement signal representing plasma ion density in said chamber, said plasma reactor further comprising a source power feedback controller, said source power feedback controller comprising:

(a) a circuit configured to furnish an ion density target value,

(b) a subtractor configured to compute an ion density error between said ion density measurement signal and said ion density target value, and

(c) a circuit configured to generate a source power control signal from said ion density error and configured to apply said source power control signal to said plasma RF source power supply so as to govern the output power of said plasma RF source power supply in a manner that tends to reduce said ion density error.

18. The plasma reactor of claim 17 wherein said circuit configured to generate a source power control signal comprises:

a circuit configured to furnish a source power feedback gain factor; and

a multiplier configured to multiply said ion density error by said source power feedback gain factor to produce said source power control signal.

19. The plasma reactor of claim 17 wherein said circuit configured to furnish an ion density target value comprises a memory containing said ion density target value.

20. The plasma reactor of claim 17 wherein said circuit configured to generate a source power control signal comprises:

a circuit configured to furnish a source power feedback gain factor; and

a multiplier configured to multiply said etch rate error by said source power feedback gain factor to produce said source power control signal.

21. The plasma reactor of claim 17 wherein said circuit configured to furnish an etch rate target value comprises a memory containing said etch rate target value.

22. The plasma reactor of claim 1 wherein said measurement instrument converts said voltage and current measurement signals into an etch rate measurement signal representing etch rate on said wafer in said chamber, said reactor further comprising a source power feedback controller, said source power feedback controller comprising:

(a) a circuit configured to furnish an etch rate target value,

(b) a subtractor configured to compute an etch rate error between said etch rate measurement signal and said etch rate target value, and

(c) a circuit configured to generate a source power control signal from said etch rate error and configured to apply said source power control signal to said plasma RF source power supply so as to govern the output power of said plasma RF source power supply in a manner that tends to reduce said etch rate error.

23. A plasma reactor comprising:

a vacuum chamber and a wafer support pedestal within said chamber for supporting a wafer to be processed within said chamber;

a process gas inlet for furnishing process gases into said chamber;

an RF source power applicator, and a plasma RF source power supply coupled to said RF source power applicator;

a plasma RF bias power supply coupled through an RF power path to said wafer support pedestal;

a memory storing sets of contours of constant performance parameter values for one of bias power and source power as a function of the other, said sets of contours comprising at least two of a set of contours of constant wafer voltage, a set of contours of constant ion density, and a set of contours of constant etch rate;

a process set point controller configured to accept user-defined target values for control parameters comprising at least two of wafer voltage, ion density and etch rate corresponding to the set of contours stored in said memory and configured to find a pair of source power and bias power values at which the corresponding ones of said contours of constant performance parameter values intersect; and

said process set point controller having an output at which said pair of source power and bias power values are coupled as power level commands to said plasma RF source power supply and said plasma RF bias power supply, respectively.

24. The plasma reactor of claim 23 wherein said sets of contours comprise different sets of said contours for different chamber pressures.

25. The plasma reactor of claim 23 wherein said sets of contours comprise different sets of contours for different values of a control parameter.

26. The plasma reactor of claim 23 further comprising:

sensor circuits configured to provide measurement signals representing voltage and current at an input end of said RF power path;

a measurement instrument for converting said measurement signals representing voltage and current into at least one of a wafer voltage measurement signal representing the voltage on a wafer supported on said wafer pedestal, an ion density measurement signal representing plasma ion density in said chamber and an etch rate measurement signal representing etch rate on said wafer; and

a constant contour generator configured to slew the power levels of said plasma RF bias power generator and said plasma RF source power generator and correlating resulting changes in at least one of said wafer voltage measurement signal, ion density measurement signal and said etch rate measurement signal so as to produce said contours of constant performance parameter values.