Method of avoiding plasma arcing during RIE etching

• US 7,247,252 B2
• Filed: 06/20/2002
• Issued: 07/24/2007
• Est. Priority Date: 06/20/2002
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yu-Chun, Jing, Shwangming, Pan, Shing-Chyang
• Primary Examiner(s): ALANKO, ANITA KAREN
• Application Number:
  US10/175,613
• Publication Number:
  US 20030235994A1
• Time in Patent Office: 1,860 Days
• Field of Search: 216/13, 216/17, 216/67, 427/535, 427/536, 438/694, 438/710, 438/723, 438/700, 438/714, 438/719, 438/724, 438/735, 438/743, 438/744
• US Class Current: 216/62
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching

Abstract

A method for avoiding plasma arcing during a reactive ion etching (RIE) process including providing a semiconductor wafer having a process surface for depositing a dielectric insulating layer; depositing at least a portion of a dielectric insulating layer to form a deposition layer according to plasma assisted chemical vapor deposition (CVD) process; treating the deposition layer portion with a hydrogen plasma treatment to reduce an electrical charge nonuniformity of the deposition layer including applying a biasing power to the semiconductor wafer; and, carrying out a subsequent reactive ion etching process.

Claims

1. A method for avoiding plasma arcing during a reactive ion etching (RIE) process comprising:

providing a semiconductor wafer comprising a process surface for depositing a dielectric insulating layer;

depositing at least a portion of the dielectric insulating layer according to plasma assisted chemical vapor deposition (CVD) process, the dielectric insulating layer comprising an electrical charge imbalance, said dielectric insulating layer selected from the group consisting of silicon dioxide, carbon doped oxide (C-oxide), organo-silicate glass (OSG), and undoped silicate glass (USG);

treating the dielectric insulating layer surface according to a hydrogen containing plasma treatment consisting of hydrogen gas and an inert gas, said plasma treatment further comprising a biasing power to reduce the electrical charge imbalance; and

,

carrying out a subsequent reactive ion etching process to etch openings in the dielectric insulating layer.

2. The method of claim 1, wherein the steps of depositing and treating are sequentially performed more than once to complete formation of a final thickness of the dielectric insulating layer.

3. The method of claim 2, wherein dielectric insulating layer thickness portions formed in each step of depositing are about equal.

4. The method of claim 1, wherein the plasma assisted CVD process is selected from the group consisting of a plasma enhanced CVD (PECVD) process and a high density plasma CVD (HDP-CVD) process.

5. The method of claim 1, wherein the dielectric insulating layer comprises a dielectric constant of less than about 3.0.

6. The method of claim 1, wherein the hydrogen containing plasma treatment consists of about 5 percent to about 20 percent by volume of hydrogen gas with a remaining portion comprising an inert gas.

7. The method of claim 1, wherein the hydrogen containing plasma treatment comprises preheating the semiconductor substrate to about 250 degrees Centigrade to about 400 degrees Centigrade;

forming a hydrogen containing plasma at a pressure of about 1 milliTorr to about 100 milliTorr;

applying an RF power of about 200 Watts to about 600 Watts; and

, applying the biasing power from about 100 to about 500 Watts.

8. The method of claim 7, wherein the hydrogen containing plasma treatment is carried out for a plasma treatment period of about 20 to about 60 seconds.

9. The method of claim 1 wherein a capping layer is formed over the dielectric insulating layer prior to carrying out the reactive ion etching process.

17. The method of claim 1, wherein the hydrogen containing plasma treatment is carried out in-situ following the step of depositing.

10. A method for avoiding plasma arcing during a reactive ion etching (RIE) process comprising:

providing a semiconductor wafer comprising a process surface for depositing a dielectric insulating layer;

depositing at least a portion of the dielectric insulating layer to form a deposition layer according to plasma assisted chemical vapor deposition (CVD) process, the dielectric insulating layer comprising an electrical charge imbalance, said dielectric layer comprising carbon doped oxide;

treating the deposition layer surface portion with a hydrogen containing plasma treatment to reduce the electrical charge imbalance wherein said hydrogen containing plasma treatment comprises hydrogen gas and an inert gas; and

,

carrying out a subsequent reactive ion etching process on the deposition layer.

11. The method of claim 10, wherein the steps of depositing and treating are sequentially performed more than once to form a final thickness of the dielectric insulating layer.

12. The method of claim 10, wherein the plasma assisted CVD process is selected from the group consisting of a plasma enhanced CVD (PECVD) process and a high density plasma CVD (HDP-CVD) process.

13. The method of claim 10, wherein the dielectric insulating layer comprises a dielectric constant of less than about 3.0.

14. The method of claim 10, wherein the hydrogen containing plasma treatment processing conditions comprise a plasma gas source mixture comprising about 5 percent to about 20 percent by volume of hydrogen gas with a remaining portion comprising an inert gas.

15. The method of claim 10, wherein the hydrogen containing plasma treatment comprises preheating the semiconductor substrate to about 250 degrees Centigrade to about 400 degrees Centigrade;

forming a hydrogen containing plasma at a pressure of about 1 milliTorr to about 100 milliTorr;

applying an RF power of about 200 Watts to about 600 Watts; and

, applying a biasing power at between about 100 and 500 Watts.

16. The method of claim 15, wherein the hydrogen containing plasma treatment is carried out for a period of about 20 to about 60 seconds.

18. A method for avoiding plasma arcing during a reactive ion etching (RIE) process comprising:

providing a semiconductor wafer comprising a process surface for depositing a dielectric insulating layer;

depositing at least a portion of the dielectric insulating layer to form a deposition layer according to plasma assisted chemical vapor deposition (CVD) process, the dielectric insulating layer comprising a negatively charged electrical charge imbalance;

treating the deposition layer surface portion with a hydrogen containing plasma treatment comprising hydrogen gas and an inert gas to reduce the electrical charge imbalance wherein said hydrogen containing plasma treatment comprises a bias power;

wherein the steps of depositing and treating are sequentially performed more than once to complete formation of a final thickness of the dielectric insulating layer; and

,

carrying out a subsequent reactive ion etching process on the deposition layer.