Silicon device on Si:C-OI and SGOI and method of manufacture

• US 7,247,534 B2
• Filed: 11/19/2003
• Issued: 07/24/2007
• Est. Priority Date: 11/19/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Dokumaci, Omer H., Gluschenkov, Oleg G.
• Primary Examiner(s): Whitehead, Jr.; Carl
• Assistant Examiner(s): MITCHELL, JAMES M
• Application Number:
  US10/715,400
• Publication Number:
  US 20050104131A1
• Time in Patent Office: 1,343 Days
• Field of Search: None
• US Class Current: 438/223
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/8086 Thin film JFET's

Abstract

A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

Claims

1. A method of manufacturing a structure, comprising the steps of:

forming shallow trench isolation (STI) in a substrate;

providing a first material on the substrate;

providing a second material on the substrate;

mixing the first material and the second material into the substrate by a thermal anneal process to form a first island and second island at a nFET region and a pFLT region, respectively; and

forming a layer of material on the first island and the second island having a lattice constant different than the first island and the second island,

wherein the STI relaxes and facilitates the relaxation of the first island and the second island.

2. The method of claim 1, wherein the first material is deposited Ge material and the second material is deposited Si:

C or C.

3. The method of claim 1, wherein the thermal anneal process takes place at about 1200 to 1350 C.

4. The method of claim 1, wherein the forming a layer of material step is growing a layer of Si material on the first island and the second island.

5. The method of claim 4, wherein the first island comprises substantially SiGe, the second island comprises substantially Si:

C and the Si layer is a strained layer.

6. The method of claim 4, wherein the Si material is placed in a tensile stress on the first island and placed in a compressive stress on the second island.

7. The method of claim 1, wherein the STI is formed of a material which has a tower viscosity as the temperature rises.

8. The method of claim 1, wherein the first material is Ge with a Ge% of approximately less than 25% to the substrate.

9. The method of claim 1, wherein the first island and the second island have a different relaxed crystal lattice.

10. The method of claim 1, wherein the STI is a high temperature stable amorphous material.

11. The method of claim 1, wherein the first material and the second material are deposited on the substrate prior to the mixing step.

12. The method of claim 1, wherein the first material and the second material are grown on the substrate prior to the mixing step.

13. The method of claim 1, wherein the second material is implanted C at a dose which produces concentrations of greater than 1-2% Si:

C upon the thermal anneal process.

14. The method of claim 1, wherein the layer of material includes selectively growing an Si epitaxial layer on the first island and the second island, the Si epitaxial layer having a different lattice constant than the first island and the second island such that the selectively grown Si epitaxial layer will strain tensilely and compressively on the first island and the second island, respectively.

15. The method of claim 1, wherein the first island has a lattice constant a≧

aSi and the second island has a lattice constant a≦

aSi.

16. The method of claim 15, wherein the first island is comprised substantially of SiGe and the second island is comprised substantially of Si:

C and an epitaxially grown layer over the SiGe island and the Si;

C layer is placed under a tensile stress and a compressive stress, respectively, by virtue of lattice matching of the epitaxially grown layer to the SiGe and Si;

C.

17. The method of claim 1, wherein the second island is comprised substantially of Si:

C and the C has a range of about 1-4% upon the thermal anneal process.