High Q inductor integration

• US 7,247,544 B1
• Filed: 04/12/2002
• Issued: 07/24/2007
• Est. Priority Date: 04/12/2002
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Drizlikh, Sergei, Francis, Thomas, Thibeault, Todd Patrick
• Primary Examiner(s): Ha; Nathan W.
• Application Number:
  US10/121,242
• Time in Patent Office: 1,929 Days
• Field of Search: 257/355, 257/724, 257/531, 257/774, 438/420, 438/629, 438/637
• US Class Current: 438/420
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In an inductor integration process, a high Q inductor is achieved by forming an AlCu inductor via prior to depositing the inductor dielectric.

Claims

1. A method of forming a via between metal layers in an integrated circuit, comprising

forming a via post by depositing a metal layer, performing a photoresist and masking step, and etching away the metal to leave the via post, and

thereafter depositing a main dielectric through which the via post extends.

2. A method of claim 1, wherein the step of depositing a metal layer is preceded by forming a first metal layer, forming a first dielectric layer on top of the first metal layer, and forming a hole in the first dielectric, and thereafter depositing said metal layer to define a second metal layer over the first dielectric to contact the first metal layer through the hole, etching back the second metal layer to define the via post, and depositing the main dielectric layer over the via post so that the via post extends through the main dielectric layer.

3. A method of claim 2, further comprising clearing the main dielectric from the via post and forming an inductor to contact the top of the via post.

4. A method of claim 3, wherein the clearing of the main dielectric from the via post includes planarizing the main dielectric and then etching back the main dielectric.

5. A method of claim 4, wherein the etching back of the main dielectric is done using a dry oxide etch step.

6. A method of claim 2, wherein the main dielectric forms a peak over the via post with troughs on either side, and the main dielectric is cleared from the via post by depositing a resist in the troughs and etching back the dielectric over the via post by means of a resist etch back.

7. A method of claim 2, wherein the second metal layer comprises AlCu.

8. A method of claim 2, wherein forming the first dielectric includes depositing a dielectric layer, and polishing the dielectric layer down to a predetermined thickness.

9. A method of claim 8, wherein the first dielectric layer is deposited to a thickness of approximately 18 kÅ

.

10. A method of claim 8, wherein the ratio of the depth of the hole as defined by the thickness of the first dielectric after polishing, to the width of the hole, is at least 1:

3.

11. A method of claim 10, wherein the ratio of the depth of the hole to the width of the hole is at least 1:

10.

12. A method of claim 2, wherein the etching back of the second metal layer to define the via includes depositing a resist on the second metal layer and selectively etching away parts of the second metal layer using a reverse via mask.