Method for fabricating a capacitor using a metal insulator metal structure

• US 7,247,572 B2
• Filed: 12/22/2003
• Issued: 07/24/2007
• Est. Priority Date: 12/24/2002
• Status: Expired due to Fees

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Jo, Bo-Yeoun
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US10/743,573
• Publication Number:
  US 20040147085A1
• Time in Patent Office: 1,310 Days
• Field of Search: 438/253, 438/396, 438/712, 257/E21.214
• US Class Current: 438/712
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer

Abstract

A method for fabricating a capacitor using a metal/insulator/metal (MIM) structure is disclosed. An example method for fabricating a capacitor using an MIM structure including a first metal layer, a dielectric layer, and a second metal layer etches the second metal layer and the dielectric layer in order and changes the etching conditions associated with the second metal layer prior to etching the dielectric layer.

Claims

1. A method for fabricating a capacitor in a metal/insulator/metal structure including a first metal layer, a dielectric layer comprising a nitride, and a second metal layer comprising Ti and TiN in order, the method comprising:

forming a photoresist pattern on the second metal layer;

etching the second metal layer with a gas mixture consisting essentially of Cl₂, CHF₃ and Ar in a ratio of 5;

1;

5, using the photoresist pattern as a mask; and

etching the dielectric layer with a gas mixture consisting essentially of Cl₂ and Ar in a ratio of 1 to 2, using the photoresist pattern as the mask, to leave a residual dielectric layer over the first metal layer in an etched part of the dielectric layer.

2. The method of claim 1, wherein etching the second metal layer comprises a first reactive ion etching process, and etching the dielectric layer comprises a second reactive ion etching process.

3. The method of claim 1, wherein a thickness of the Ti is 300 to 700Å

and a thickness of the TiN is 1300 to 1700Å

.

4. The method of claim 1, wherein a total thickness of the second metal layer is 1600 to 2400Å

.

5. The method of claim 1, wherein a thickness of the dielectric layer is 400 to 800Å

.

6. The method of claim 1, wherein the first metal layer comprises a first Ti/TiN stack, an AlCu layer and a second Ti/TiN stack in order.

7. The method of claim 1, wherein, etching the second metal layer comprises etching the second metal layer for 45 to 55 seconds.

8. The method of claim 1, wherein etching the second metal layer comprises generating a plasma at a pressure of 8 mTorr and a power of 900 W and applying a bias power of more than 150 W.

9. The method of claim 1, wherein an etching time associated with the dielectric layer is between about 10 to 15% of an etching time associated with the second metal layer.

10. The method of claim 1, wherein etching the dielectric layer comprises etching the dielectric layer for 4.5 to 8 seconds.

11. The method of claim 1, wherein etching the dielectric layer comprises generating a plasma is generated under a pressure of 8 mTorr and an application power of 900 W and applying a bias power of more than 150 W.

12. The method of claim 1, wherein a thickness of the photoresist pattern is 11,000 to 15,000Å

.

13. The method of claim 1, wherein the dielectric layer comprises silicon nitride.

14. The method of claim 1, wherein the residual dielectric layer comprises a continuous residual dielectric layer over the first metal layer.