Segmented channel MOS transistor

• US 7,247,887 B2
• Filed: 07/01/2005
• Issued: 07/24/2007
• Est. Priority Date: 07/01/2005
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Moroz, Victor, King, Tsu-Jae
• Primary Examiner(s): Potter; Roy Karl
• Application Number:
  US11/173,237
• Publication Number:
  US 20070001237A1
• Time in Patent Office: 753 Days
• Field of Search: 257/139
• US Class Current: 257/139
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

Claims

1. A transistor comprising:

a source;

a drain;

a channel region between the source and the drain; and

a gate over the channel region,

wherein the channel region comprises a plurality of semiconductor ridges connecting the source and the drain,

wherein the plurality of semiconductor ridges are separated in part by insulation material, and

wherein the plurality of semiconductor ridges are formed on an elevated base region on a substrate.

2. The transistor of claim 1, wherein each of the plurality of semiconductor ridges has a ridge height above the elevated base region, and

wherein a height of the elevated base region above adjacent portions of the substrate is equal to at least the ridge height.

3. The transistor of claim 2, wherein the height of the elevated base region above the adjacent portions of the substrate is at least five times the ridge height.

4. The transistor of claim 1, further comprising a plurality of gate dielectrics, each of the plurality of gate dielectrics being formed over a top portion of one of the plurality of semiconductor ridges, the plurality of gate dielectrics separating the top portion of each of the plurality of semiconductor ridges from the gate.

5. The transistor of claim 4, wherein each of the plurality of gate dielectrics wraps around the top portion of one of the plurality of semiconductor ridges, and

wherein the gate wraps around the top portion of each of the plurality of semiconductor ridges over the plurality of gate dielectrics.

6. The transistor of claim 1, wherein each of the plurality of semiconductor ridges includes a subsurface heavily doped region.

7. The transistor of claim 6, further comprising a plurality of gate dielectrics, each of the plurality of gate dielectrics being formed over a top portion of one of the plurality of semiconductor ridges, the plurality of gate dielectrics separating the top portion of each of the plurality of semiconductor ridges from the gate,

wherein each of the plurality of gate dielectrics wraps around the top portion of one of the plurality of semiconductor ridges,

wherein the gate wraps around the top portion of each of the plurality of semiconductor ridges over the plurality of gate dielectrics, and

wherein the sub-surface heavily doped region in each of the plurality of semiconductor ridges reaches no more than 50% of maximum dopant concentration within the top portion of the each of the plurality of semiconductor ridges.

8. The transistor of claim 6, wherein the subsurface heavily doped region comprises a pulse doped region.

9. The transistor of claim 6, wherein the subsurface heavily doped region comprises one of a halo doped region and a pocket doped region.

10. The transistor of claim 1, wherein the source comprises a first region doped to a first depth below the top surfaces of the plurality of semiconductor ridges,

wherein the drain comprises a second region doped to a second depth below the top surfaces of the plurality of semiconductor ridges, and

wherein the insulation material reaches a third depth below the top surfaces of the plurality of semiconductor ridges, the third depth being greater than the first depth and the second depth.

11. The transistor of claim 1, wherein the source comprises a first region doped to a first depth below the top surfaces of the plurality of semiconductor ridges,

wherein the drain comprises a second region doped to a second depth below the top surfaces of the plurality of semiconductor ridges, and

wherein the insulation material reaches a third depth below the top surfaces of the plurality of semiconductor ridges, the third depth being less than the first depth and the second depth.

12. The transistor of claim 1, further comprising:

a first sidewall spacer; and

a second sidewall spacer, the gate being between the first sidewall spacer and the second sidewall spacer,

wherein the source comprises a first lightly doped extension under the first sidewall spacer, and

wherein the drain comprises a second lightly doped extension under the second sidewall spacer.

13. The transistor of claim 1, wherein the source comprises a source extension adjacent to the channel region,

wherein the drain comprises a drain extension adjacent to the channel region, and

wherein the source extension and the drain extension comprise a metal-semiconductor compound.

14. The transistor of claim 1, wherein the plurality of semiconductor ridges are formed on an insulating layer.

15. The transistor of claim 1, wherein the source comprises a first set of discrete structures, wherein a quantity of the first set of discrete structures are continuous with the plurality of semiconductor ridges, and

wherein the drain comprises a second set of discrete structures, wherein the quantity of the second set of discrete structures are continuous with the plurality of semiconductor ridges.

16. The transistor of claim 15, wherein the source further comprises a first semiconductor region formed over the first set of discrete structures,

wherein the drain further comprises a second semiconductor region formed over the second set of discrete structures,

wherein the first semiconductor region and the second semiconductor region comprise a first semiconductor material, and

wherein the first set of discrete structures and the second set of discrete structures comprise a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

17. The transistor of claim 15, further comprising a stressed capping layer formed over the gate, the source, and the drain for inducing stress within the plurality of semiconductor ridges.

18. A transistor comprising:

a source;

a drain;

a channel region between the source and the drain; and

a gate over the channel region,

wherein the channel region comprises a plurality of semiconductor ridges connecting the source and the drain, the plurality of semiconductor ridges being separated in part by insulation material, and

wherein each of the plurality of semiconductor ridges includes a sub-surface heavily doped channel region.

19. The transistor of claim 18, further comprising a plurality of gate dielectrics, each of the plurality of gate dielectrics being formed over a top portion of one of the plurality of semiconductor ridges, the plurality of gate dielectrics separating the top portion of each of the plurality of semiconductor ridges from the gate.

20. The transistor of claim 18, wherein each of the plurality of gate dielectrics wraps around the top portion of one of the plurality of semiconductor ridges, and

wherein the gate wraps around the top portion of each of the plurality of semiconductor ridges over the plurality of gate dielectrics.

21. The transistor of claim 20, wherein the sub-surface heavily doped region in each of the plurality of semiconductor ridges reaches at least 50% of maximum dopant concentration within the top portion of the each of the plurality of semiconductor ridges.

22. The transistor of claim 21, wherein the sub-surface heavily doped region in each of the plurality of semiconductor ridges reaches at least 50% of maximum dopant concentration at least 5 nm below the top surface of the each of the plurality of semiconductor ridges.

23. The transistor of claim 20, wherein the sub-surface heavily doped region in each of the plurality of semiconductor ridges reaches at least 50% of maximum dopant concentration below the top portion of the each of the plurality of semiconductor ridges.

24. The transistor of claim 18, wherein the source comprises a first region doped to a first depth below the top surfaces of the plurality of semiconductor ridges,

wherein the drain comprises a second region doped to a second depth below the top surfaces of the plurality of semiconductor ridges, and

wherein the insulation material reaches a third depth below the top surfaces of the plurality of semiconductor ridges, the third depth being greater than the first depth and the second depth.

25. The transistor of claim 18, wherein the source comprises a first region doped to a first depth below the top surfaces of the plurality of semiconductor ridges,

wherein the drain comprises a second region doped to a second depth below the top surfaces of the plurality of semiconductor ridges, and

wherein the insulation material reaches a third depth below the top surfaces of the plurality of semiconductor ridges, the third depth being less than the first depth and the second depth.

26. The transistor of claim 18, further comprising:

a first sidewall spacer; and

a second sidewall spacer, the gate being between the first sidewall spacer and the second sidewall spacer,

wherein the source comprises a first lightly doped extension under the first sidewall spacer, and

wherein the drain comprises a second lightly doped extension under the second sidewall spacer.

27. The transistor of claim 18, wherein the plurality of semiconductor ridges are formed on an insulating layer.

28. The transistor of claim 18, wherein the source comprises a first set of discrete structures, wherein a quantity of the first set of discrete structures are continuous with the plurality of semiconductor ridges, and

wherein the drain comprises a second set of discrete structures, wherein the quantity of the second set of discrete structures are continuous with the plurality of semiconductor ridges.

29. The transistor of claim 18, further comprising a stressed capping layer over the gate, the source, and the drain for inducing a stress within the plurality of semiconductor ridges.

30. The transistor of claim 18, further comprising a gate dielectric layer over a top surface of each of the plurality of semiconductor ridges,

wherein the sub-surface heavily doped region in each of the plurality of semiconductor ridges reaches at least 50% of maximum dopant concentration at least 5 nm below the top surface of the each of the plurality of semiconductor ridges.