Structures and methods for making strained MOSFETs

• US 7,247,912 B2
• Filed: 01/05/2004
• Issued: 07/24/2007
• Est. Priority Date: 01/05/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Zhang, Ying, Bedell, Steven W., Zhu, Hiulong
• Primary Examiner(s): Vu; David
• Application Number:
  US10/707,690
• Publication Number:
  US 20050145954A1
• Time in Patent Office: 1,296 Days
• Field of Search: 257/192, 257/347, 257/353, 257/401, 257/619, 257/623, 257/E21.422, 257/E29.056, 257/E29.275, 257/E29.298, 257/E29.299
• US Class Current: 257/353
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A method and device providing a strained Si film with reduced defects is provided, where the strained Si film forms a fin vertically oriented on a surface of a non-conductive substrate. The strained Si film or fin may form a semiconductor channel having relatively small dimensions while also having few defects. The strained Si fin is formed by growing Si on the side of a relaxed SiGe block. A dielectric gate, such as, for example, an oxide, a high “k” material, or a combination of the two, may be formed on a surface of the strained Si film. Additionally, without substantially affecting the stress in the strained Si film, the relaxed SiGe block may be removed to allow a second gate oxide to be formed on the surface previously occupied by the relaxed SiGe block. Accordingly, a semiconductor device having a strained Si fin vertically oriented on a non-conductive substrate may be formed where the strained Si film is oriented such that it may form a channel of small dimensions allowing access to both sides and top in order to from single gate, double gate, or more gate MOSFETs and finFETs with a channel having a reduced number of defects and/or reduced dimensions.

Claims

1. A semiconductor structure, comprising:

a channel having a fin of strained Si vertically oriented on a non-conductive substrate;

a gate comprising at least one of an oxide and a high k material formed on a first side, a second side and a top of the strained Si film;

a poly silicon layer adjacent the at least one of an oxide and a high k material formed on the first side, the second side and the top of the strained Si film; and

an oxide layer partially formed on the poly silicon layer.

2. The structure of claim 1, wherein the strained Si film is between about 50 Å

and 200 Å

thick.

3. The structure of claim 1, wherein the strained Si film is epitaxially grown on a block of relaxed SiGe, wherein the relaxed SiGe comprises a range of Ge ranging from about 0% to about 100%.

4. The structure of claim 1, wherein the Si film is a low defect strained Si film.

5. The structure of claim 1, further comprising a second poly silicon layer over the oxide layer and the poly silicon layer.

6. The structure of claim 1, wherein the oxide layer is formed substantially in a vertical orientation.

7. The structure of claim 1, wherein the oxide layer is formed on a side wall of the fin.

8. A semiconductor structure, comprising:

strained Si vertically oriented fin on a non-conductive substrate;

an oxide layer surrounding the Si vertically oriented fin;

a polysilicon layer covering the oxide material surrounding the Si vertically oriented fin; and

an oxide layer partially formed on the poly silicon layer;

polysilicon spacer on the oxide layer; and

a third polysilicon layer formed over the polysilicon spacers and the polysilicon layer.