Chip package with capacitor

• US 7,247,932 B1
• Filed: 05/19/2000
• Issued: 07/24/2007
• Est. Priority Date: 05/19/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Peng, Bryan
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US09/573,955
• Time in Patent Office: 2,622 Days
• Field of Search: 257/700, 257/701, 257/754, 257/686, 257/685, 257/723, 257/777, 257/778, 257/737, 257/738, 257/739, 257/698, 257/691, 257/203, 257/204, 257/208, 257/211, 257/210, 257/724, 257/528, 257/532, 257/E23.013, 257/E25.011, 257/E25.03, 257/E23.004, 257/E23.067, 257/E23.079, 257/784, 257/773, 257/734
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/09309 : Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

Claims

1. A chip package comprising:

a circuit substrate;

a first chip over said circuit substrate;

a second chip over said circuit substrate;

a first bump under said circuit substrate;

a second bump under said circuit substrate;

a third bump between said first chip and said circuit substrate, wherein said third bump has a height less than that of said first bump; and

a first passive device under said circuit substrate, wherein said first passive device is between said first and second bumps.

2. The chip package of claim 1, wherein said first passive device is under said first chip.

3. The chip package of claim 1 further comprising a fourth bump connecting said second chip and said circuit substrate.

4. The chip package of claim 1 further comprising a second passive device over said circuit substrate.

5. The chip package of claim 1, wherein said first passive device comprises a capacitor.

6. The chip package of claim 1, wherein said circuit substrate comprises a printed circuit board.

7. The chip package of claim 1, wherein said first bump comprises solder.

8. The chip package of claim 1, wherein said first bump comprises solder, and said second bump comprises solder.

9. The chip package of claim 1, wherein the distance between said first passive device and said first bump is less than that between said first passive device and said second bump.

30. The chip package of claim 4, wherein said second passive device comprises a capacitor.

10. A chip package comprising:

a circuit substrate;

a first chip over said circuit substrate;

a first bump under said circuit substrate;

a second bump connecting said first chip and said circuit substrate, wherein said second bump has a height less than that of said first bump;

a first passive device over said circuit substrate;

a second passive device under said circuit substrate.

11. The chip package of claim 10 further comprising a second chip over said circuit substrate.

12. The chip package of claim 10, wherein said second passive device is under said first chip.

13. The chip package of claim 10, wherein said first bump comprises solder.

14. The chip package of claim 10, wherein said first passive device comprises a capacitor.

15. The chip package of claim 10, wherein said first passive device comprises a capacitor and said second passive device comprises a capacitor.

16. The chip package of claim 10, wherein said circuit substrate comprises a printed circuit board.

31. The chip package of claim 10, wherein said second bump comprises solder.

17. A chip package comprising:

a circuit substrate comprising a via connector extending in a vertical direction and a ground plane spreading in a horizontal level and contacting said via connector;

a first chip joined with said circuit substrate;

a second chip joined with said circuit substrate;

a capacitor connected to said circuit substrate; and

a connecting portion over said via connector and over said circuit substrate, wherein said connecting portion connects said via connector and said capacitor.

18. The chip package of claim 17, wherein said circuit substrate further comprises a power plane connected to said capacitor.

32. The chip package of claim 17 further comprising a bump between said first chip and said circuit substrate.

33. The chip package of claim 32, wherein said bump comprises solder.

34. The chip package of claim 17 further comprising a first bump between said first chip and said circuit substrate, and a second bump between said second chip and said circuit substrate.

35. The chip package of claim 34, wherein said first and second bumps comprise solder.

36. The chip package of claim 17, wherein said first and second chips are over said circuit substrate, and said capacitor is under said circuit substrate.

37. The chip package of claim 17, wherein said first and second chips and said capacitor are over said circuit substrate.

38. The chip package of claim 17 further comprising a first bump joined with said circuit substrate, and a second bump joined with said circuit substrate, wherein said capacitor is between said first and second bumps.

39. The chip package of claim 38, wherein said first and second bumps comprise solder.

19. A chip package comprising:

a circuit substrate comprising a via connector extending in a vertical direction and a ground plane spreading in a horizontal level and contacting said via connector;

a first bump under said circuit substrate, wherein said first bump comprises solder;

a first chip over said circuit substrate;

a capacitor over said circuit substrate; and

a connecting portion over said via connector, wherein said connecting portion connects said via connector and said capacitor.

20. The chip package of claim 19, wherein said circuit substrate further comprises a power plane connected to said capacitor.

40. The chip package of claim 19 further comprising a second bump between said first chip and said circuit substrate.

41. The chip package of claim 40, wherein said second bump comprises solder.

42. The chip package of claim 40, wherein said first bump has a height greater than that of said second bump.

43. The chip package of claim 19 further comprising a second chip over said circuit substrate.

44. The chip package of claim 43 further comprising a second bump between said second chip and said circuit substrate.

45. The chip package of claim 44, wherein said second bump comprises solder.

21. A chip package comprising:

a circuit substrate consisting of multiple circuit layers arranged in parallel, the topmost one of said multiple circuit layers comprising a trace, a first contact and a second contact, said trace said first and second contacts, wherein said trace is at the same horizontal level as said first and second contacts are;

a first chip over said circuit substrate;

a first bump between said first chip and said first contact, wherein said first bump is in contact with said first contact; and

a passive device over said circuit substrate, wherein said passive device is connected to said second contact.

22. The chip package of claim 21 further comprising a second chip over said circuit substrate, wherein the topmost one of said multiple circuit layers further comprises a third contact connected to said first and second contacts and to said second chip.

23. The chip package of claim 21, wherein said multiple circuit layers comprise a power plane connected to said trace.

24. The chip package of claim 21, wherein said multiple circuit layers comprise a ground plane connected to said trace.

25. The chip package of claim 21 further comprising a first bump comprising solder.

46. The chip package of claim 22 further comprising a second bump between said second chip and said third contact.

47. The chip package of claim 46, wherein said second bump comprises solder.

48. The chip package of claim 21 further comprising a second bump under said circuit substrate.

49. The chip package of claim 48, wherein said second bump comprises solder.

50. The chip package of claim 21, wherein said passive device comprises a capacitor.

51. The chip package of claim 22, wherein said passive device is between said first and second chips.

26. A chip package comprising:

a circuit substrate;

a first chip over said circuit substrate;

a second chip over said circuit substrate; and

a passive device over said circuit substrate, wherein said passive device is between said first and second chips, and wherein said circuit substrate comprises a portion connecting said first and second chips and said passive device.

27. The chip package of claim 26 further comprising a bump between said first chip and said circuit substrate.

28. The chip package of claim 27, wherein said bump comprises solder.

29. The chip package of claim 26 further comprising a bump under said circuit substrate.

52. The chip package of claim 29, wherein said bump comprises solder.

53. The chip package of claim 26 further comprising a first bump between said first chip and said circuit substrate, and a second bump between said second chip and said circuit substrate.

54. The chip package of claim 26, wherein said passive device comprises a capacitor.

55. The chip package of claim 26, wherein said circuit substrate comprises a power plane connected to said portion.

56. The chip package of claim 26, wherein said circuit substrate comprises a ground plane to said portion.