Chip carrier with oxidation protection layer

• US 7,247,951 B2
• Filed: 12/23/2004
• Issued: 07/24/2007
• Est. Priority Date: 09/10/2004
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Ho, Kwun-Yao, Kung, Moriss
• Primary Examiner(s): Williams; Alexander Oscar
• Application Number:
  US11/022,244
• Publication Number:
  US 20060055023A1
• Time in Patent Office: 943 Days
• Field of Search: 257/E23.06, 257/E23.055, 257/E23.056, 257/E23.092, 257/E23.012, 257/E23.124, 257/668, 257/700, 257/701, 257/758, 257/784, 257/786, 257/692, 257/737, 257/738
• US Class Current: 257/786
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H05K 2201/0317 : Thin film conductor layer; Thin film passive component
• CPC Class Codes: H05K 2203/049 : Wire bonding
• CPC Class Codes: H05K 2203/072 : Electroless plating, e.g. finish plating or initial plating
• CPC Class Codes: H05K 2203/073 : Displacement plating, substitution plating or immersion plating, e.g. for finish plating
• CPC Class Codes: H05K 3/244 : Finish plating of conductors, especially of copper conductors, e.g. for pads or lands selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3457, e.g. by plating H05K3/3473
• CPC Class Codes: H05K 3/28 : Applying non-metallic protective coatings H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673

Abstract

A chip carrier comprising a laminated layer and an oxidation protection layer is provided. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection film on the surface of bonding finger pads or other contacts formed by deploying a simple, fast film-coating technique. Therefore, there is no need to plate a Ni/Au layer on the bonding pads or contacts using expensive electroplating equipment for preventing oxidation and there is no need to fabricate plating lines on the chip carrier or reserve space for laying out the plating lines. Thus, the cost for fabricating the chip carrier is reduced, the effective area of the chip carrier is increased and the electrical performance of the chip carrier is improved.

Claims

1. A chip carrier for supporting a chip, comprising:

a laminated layer having a non-plating line design, a top surface and a bottom surface, wherein the laminated layer has at least a bonding finger pad on the top surface and the bonding finger pad is electrically connected to the chip through a bonding wire; and

an oxidation protection layer covering the bonding finger pad, wherein the oxidation protection layer is a non-electrolytic metallic coating, and wherein the oxidation protection layer has a thickness smaller than or equal to 0.5 μ

m, and the material constituting the oxidation protection layer is selected from a group consisting of cobalt, zinc, tin, and bismuth; and

wherein the bonding wire penetrates the oxidation protection layer and directly connects the bonding finger pad.

2. The chip carrier of claim 1, wherein the chip carrier further comprises a soldering mask layer covering the top surface of the laminated layer and having an opening that exposes a portion of the bonding finger pad.

3. The chip carrier of claim 1, wherein the material constituting the bonding wire is selected from a group consisting of aluminum, copper, nickel, titanium, tungsten, platinum, silver and palladium.

4. The chip carrier of claim 1, wherein the bonding finger pad comprises a copper pad or an aluminum pad.

5. A chip package structure, comprising:

a chip;

a chip carrier for supporting the chip and electrically connecting to the chip, having;

a laminated layer having a non-plating line design, a top surface and a bottom surface, wherein the laminated layer has at least a bonding finger pad on the top surface, wherein the bonding finger pad comprises a copper pad or an aluminum pad;

an oxidation protection layer covering the bonding finger pad, wherein the oxidation protection layer is a non-electrolytic metallic coating, and the material constituting the oxidation protection layer is selected from a group consisting of cobalt, zinc, tin, and bismuth; and

at least a bonding wire connecting the chip and the bonding finger pad, wherein the bonding wire penetrates the oxidation protection layer and directly connects the bonding finger pad.

6. The chip package structure of claim 5, wherein the laminated layer further comprises at least a dielectric layer such that the bonding finger pad is disposed over the dielectric layer.

7. The chip package structure of claim 5, further comprises a soldering mask layer covering the top surface of the laminated layer and having an opening that exposes a portion of the bonding finger pad.

8. The chip package structure of claim 5, wherein the material constituting the bonding wire is selected from a group consisting of aluminum, copper, nickel, titanium, tungsten, platinum, silver and palladium.

9. A chip package structure, comprising:

a chip;

a chip carrier for supporting the chip and electrically connecting to the chip, having;

a laminated layer having a non-plating line design, a top surface and a bottom surface, wherein the laminated layer has at least a bonding finger pad on the top surface, wherein the bonding finger pad comprises a copper pad or an aluminum pad;

an oxidation protection layer covering the bonding finger pad, wherein the oxidation protection layer is an organic oxidation protection film; and

at least a bonding wire connecting the chip and the bonding finger pad, wherein the bonding wire penetrates the oxidation protection layer and directly connects the bonding finger pad.

10. The chip package structure of claim 9, wherein the laminated layer further comprises at least a dielectric layer such that the bonding finger pad is disposed over the dielectric layer.

11. The chip package structure of claim 9, further comprises a soldering mask layer covering the top surface of the laminated layer and having an opening that exposes a portion of the bonding finger pad.

12. The chip package structure of claim 9, wherein the material constituting the bonding wire is selected from a group consisting of aluminum, copper, nickel, titanium, tungsten, platinum, silver and palladium.

13. The chip package structure of claim 9, wherein the organic oxidation protection film is an organic surface preservation (OSP) or a self-assembly monolayer (SAM).