Multi-mode digital bias control for enhancing power amplifier efficiency

• US 7,248,111 B1
• Filed: 04/14/2005
• Issued: 07/24/2007
• Est. Priority Date: 04/14/2005
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Anadigics Incorporated (Coherent Corp.)
• Inventors: Arell, Thomas William, Singh, Mahendra, Xu, Sheldon, Khatibzadeh, Mohammed Ali
• Primary Examiner(s): NGUYEN, KHANH V
• Application Number:
  US11/106,254
• Time in Patent Office: 831 Days
• Field of Search: None
• US Class Current: 330/133
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 3/191 Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/343 with semiconductor devices only
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03G 3/3047 for intermittent signals, e.g. burst signals

Abstract

A power amplifier with a multi-mode digital bias control circuit is provided. The power amplifier utilizes a complementary reference voltage generation circuit and a bias current-control circuit to generate a plurality of bias current levels for different output power levels. In an embodiment of the present invention, the power amplifier circuit is connected to a reference voltage and two control signals. Depending on the desired output power level, the control signals set the corresponding bias current in the amplifying transistors, to ensure sufficient linearity. The power amplifier is capable of operating at a very low quiescent current level, for example, 5 mA. As a result, a significant improvement in the power amplifier'"'"'s overall efficiency is achieved, and the battery talk time of a wireless communication device is increased. The invention finds application in wireless communication devices such as CDMA, WCDMA, EDGE and WLAN mobile devices.

Claims

1. A power amplifier including multi-mode digital bias control circuitry, the power amplifier generating four different bias current levels in response to a combination of two control signals, the power amplifier comprising:

a. a complementary reference voltage generation circuit having a first input connected to a first reference voltage, and a second input connected to the first control signal;

b. a bias current control circuit having an input connected to the second control signal;

c. a low power bias circuit having a first input connected to a first output of the complementary reference voltage generation circuit, and a second input connected to a first output of the bias current control circuit;

d. a first stage high power bias circuit having a first input connected to a second output of the complementary voltage reference generation circuit, and a second input connected to a second output of the bias current control circuit; and

e. a second stage high power bias circuit having a first input connected to the second output of the complementary voltage reference generation circuit, and a second input connected to a third output of the bias current control circuit.

2. The power amplifier of claim 1, wherein the complementary reference voltage generation circuit has two outputs, enabling or disabling bias circuits of low power channel and high power channel:

a. a first output connected to the low power bias circuit; and

b. a second output connected to the first stage high power bias circuit and the second stage high power bias circuit.

3. The power amplifier of claim 1, wherein the multi-mode digital bias control circuitry sets a bias current for the power amplifier transmitting at a high-power level with sufficient linearity, when the first control signal is at logic low and the second control signal is set at logic low.

4. The power amplifier of claim 1, wherein the multi-mode digital bias control circuitry sets a bias current for the power amplifier transmitting at a medium high-power level with sufficient linearity, when the first control signal is at logic low and the second control signal is set at logic high.

5. The power amplifier of claim 1, wherein the multi-mode digital bias control circuitry sets a bias current for the power amplifier transmitting at a medium-low power level with sufficient linearity, when the first control signal is at logic high and the second control signal is set at logic low.

6. The power amplifier of claim 1, wherein the multi-mode digital bias control circuitry sets a bias current for the power amplifier transmitting at a low power level with sufficient linearity, when the first control signal is at logic high and the second control signal is set at logic high.

7. The power amplifier of claim 2, wherein the complementary reference voltage generation circuit shuts down both the high power channel and the low power channel when external reference voltage is at logic low.

8. The power amplifier of claim 1, wherein the bias current control circuit controls bias currents in:

a. the low power bias circuit;

b. the first stage high power bias circuit; and

c. the second stage high power bias circuit.

9. The power amplifier of claim 1, wherein the complementary reference voltage generation circuit generates a pair of high and low voltages when an external reference voltage is on, enabling or disabling the high power channel or low power channel, the complementary reference voltage generation circuit comprising:

a. a first resistor having a first terminal connected to the first control signal;

b. a first transistor having a base connected to a second terminal of the first resistor, and an emitter connected to ground;

c. a second resistor having a first terminal connected to a collector of the first transistor, and a second terminal connected to the first reference voltage;

d. a third resistor having a first terminal connected to the collector of the first transistor;

e. a second transistor having a base connected to a second terminal of the third resistor, and an emitter connected to the ground;

f. a fourth resistor having a first terminal connected to the first reference voltage and a second terminal connected to a collector of the second transistor;

g. a fifth resistor having a first terminal connected to the collector of the first transistor;

h. a first field effect transistor having a gate connected to a second terminal of the fifth resistor, a drain connected to the first reference voltage, and a source connected to the low power bias circuit;

i. a sixth resistor having a first terminal connected to the collector of the second transistor; and

j. a second field effect transistor having a gate connected to a second terminal of the sixth resistor, a drain connected to the first reference voltage, and a source connected to both the first stage high power bias circuit and the second stage high power bias circuit.

10. The power amplifier of claim 1, wherein the bias current control circuit enables control of bias current in the low power bias circuit, the first stage high power bias circuit and the second stage high power bias circuit, the bias current control circuit comprising

a. a first resistor having a first terminal connected to the second control signal;

b. a first transistor having a base connected to a second terminal of the first resistor, and an emitter connected to the ground;

c. a second resistor having a first terminal connected to a collector of the first transistor, and a second terminal, wherein bias current in low power bias circuit is controlled by an output signal at the second terminal;

d. a third resistor having a first terminal connected to the second control signal;

e. a second transistor having a base connected to a second terminal of the third resistor, and an emitter connected to the ground;

f. a fourth resistor having a first terminal connected to a collector of the second transistor, and a second terminal, wherein bias current in the first stage high power bias circuit is controlled by an output signal at the second terminal; and

g. a fifth resistor having a first terminal connected to a collector of the second transistor, and a second terminal, wherein bias current in the second stage high power bias circuit is controlled by an output signal at the second terminal.

11. A power amplifier including multi-mode digital bias control circuitry, the power amplifier capable of generating four different bias current levels in response to a combination of two control signals, the power amplifier comprising:

a. a low power bias enable circuit, the low power bias enable circuit having a first input connected to a first reference voltage, and a second input connected to the first control signal;

b. a high power bias enable circuit, the high power bias enable circuit having a first input connected to the first reference voltage, and a second input connected to the first control signal controls the first stage high power bias circuit and the second stage high power bias circuit;

c. a bias current control circuit having an input connected to the second control signal;

d. a low power bias circuit having a first input connected to output of the low power bias enable circuit, and a second input connected to a first output of the bias current control circuit;

e. a first stage high power bias circuit having a first input connected to a first output of the high power bias enable circuit, and a second input connected to a second output of the bias current control circuit; and

f. a second stage high power bias circuit having a first input connected to a second output of the high power bias enable circuit, and a second input connected to a third output of the bias current control circuit.

12. The power amplifier bias control circuitry of claim 11, wherein the low power bias enable circuit further controls at least one amplifying transistor in a low power channel.

13. The power amplifier bias control circuitry of claim 11, wherein the high power bias enable circuit further controls at least one amplifying transistor in a high power channel.

14. A power amplifier circuit having a first input node connected to a first reference voltage, a second input node connected to a ground, a first control input node connected to a first control signal, and a second control input node connected to a second control signal, the power amplifier circuit comprising:

a. a complementary reference voltage generation circuit having a first input connected to a first reference voltage, and a second input connected to the first control signal;

b. a bias current control circuit having an input connected to the first control signal;

c. a low power bias circuit having a first input connected to a first output of the complementary reference voltage generation circuit, and a second input connected to a first output of the bias current control circuit;

d. a first stage high power bias circuit having a first input connected to a second output of the complementary voltage reference generation circuit, and a second input connected to a second output of the bias current control circuit;

e. a second stage high power bias circuit having a first input connected to the second output of the complementary voltage reference generation circuit, and a second input connected to a third output of the bias current control circuit;

f. a high power input impedance matching circuit having a first node connected to an input signal and a second node connected to an output node of the first stage high power bias circuit, the high power input impedance matching circuit matching impedance between the input signal and an output signal of the first stage high power bias circuit;

g. a low power input impedance matching circuit having a first node connected to an input signal and a second node connected to an output node of the low power bias circuit, the low power input impedance matching circuit matching impedance between the input signal and an output signal of the low power bias circuit;

h. a first transistor having a base connected to the output of the first stage high power bias circuit, and an emitter connected to the ground;

i. an inter-stage impedance matching circuit having a first node connected to a collector of the first transistor and a second node connected to an output of the second stage high power bias circuit, the inter-stage impedance matching circuit matching impedance between a signal at the collector of the first transistor and an output signal of the second stage high power bias circuit;

j. a second transistor having a base connected to the output of the second stage high power bias circuit, and an emitter connected to the ground;

k. a third transistor having a base connected to the output of the low power bias circuit, an emitter connected to the ground;

i. a high power output impedance matching circuit having a first node connected to a collector of the second transistor and a second node connected to an output node, the high power output impedance matching circuit matching impedance between a signal at the collector of the second transistor and an output signal of the power amplifier circuit;

m. a field effect transistor having source connected to the collector of the second transistor;

n. a low power output impedance matching circuit having a first node connected to a collector of the third transistor and a second node connected to a drain of the field effect transistor; and

o. a resistor having a first terminal connected to the gate of the field effect transistor, and a second terminal connected to the second input of the complementary reference voltage generation circuit.