Stacked transistor method and apparatus

• US 7,248,120 B2
• Filed: 06/23/2004
• Issued: 07/24/2007
• Est. Priority Date: 06/23/2004
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Cable, James S.
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US10/875,405
• Publication Number:
  US 20050285684A1
• Time in Patent Office: 1,126 Days
• Field of Search: 330/311, 330/277
• US Class Current: 330/311
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

A method and apparatus is described for controlling conduction between two nodes of an integrated circuit via a stack of FETs of common polarity, coupled in series. In an RF Power Amplifier (PA) having appropriate output filtering, or in a quad mixer, stacks of two or more FETs may be used to permit the use of increased voltages between the two nodes. Power control for such RF PAs may be effected by varying a bias voltage to one or more FETs of the stack. Stacks of three or more FETs may be employed to control conduction between any two nodes of an integrated circuit.

Claims

1. An integrated RF Power Amplifier (PA) circuit, comprising:

a) an input node to accept an input signal with respect to a reference voltage Vref, coupled to a gate G1 of a first FET M1;

b) a plurality of additional FETs M2 to Mn having corresponding gates G2 to Gn and a same polarity as M1 and coupled in series with M1 to form a control circuit configured to control conduction between the reference voltage and an output drive node, wherein FETs M2 to Mn are each enslaved to M1;

c) an output coupling capacitor, coupling the output drive node to an output load node; and

d) a corresponding predominantly capacitive element connected directly between each gate, G2 to Gn, and Vref.

2. The integrated circuit of claim 1, further comprising (d) an output power control input node coupled to a power controlling FET that is coupled in series connection with M1.

3. The integrated circuit of claim 2, wherein the power controlling FET is disposed between the reference voltage and a power supply voltage external to the PA.

4. The integrated circuit of claim 2, wherein the power controlling FET is one of the FETs M2 to Mn.

5. The integrated circuit of claim 1, further comprising a low-pass filter disposed in series with the output coupling capacitor between the output drive node and the output load node.

6. An integrated RF Power Amplifier (PA) circuit, comprising:

a) an input node to accept an input signal with respect to a reference voltage Vref, coupled to a gate G1 of a first FET M1;

b) a plurality of additional FETs M2 to Mn having a same polarity as M1 and coupled in series with M1 to form a control circuit configured to control conduction between the reference voltage and an output drive node, wherein FETs M2 to Mn are each enslaved to M1;

c) an output coupling capacitor coupling the output drive node to an output load node; and

(d) a shunt resonant circuit coupled between the output drive node and the reference voltage and configured to have a minimal impedance at a frequency that is a harmonic of a center operation frequency F₀ of the PA.

7. The integrated circuit of claim 6, further comprising a plurality of shunt resonant circuits (d).

8. An integrated circuit including a multiple-FET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref, the integrated circuit comprising:

a) a series stack of J same-polarity FETs M_N, N an integer between 1 and J and J an integer 3 or greater, each FET M_N having a source S_N, a gate G_N and a drain D_N,

b) an input signal node coupled to the gate G₁ of a signal-input FET M₁ of the FET stack;

c) for 0<

N<

J, a series coupling between each drain D_N and the source S_(N+1) of a next higher FET M_(N+1) of the FET stack;

d) for 1<

N≦

J, a gate coupling element that is predominantly capacitive connected directly between between each gate G_N and Vref, in a configuration enslaving each FET M_(N+1) to M₁ so as to conduct substantially concurrently with, and under control of, conduction in M₁;

e) a source coupling for the FET stack between S₁ and Vref; and

f) a drain coupling for the FET stack between D_J and Vdrive.

9. The integrated circuit of claim 8, wherein a peak value of voltage on Vdrive with respect to Vref, Vdrive(peak), is divided approximately uniformly across all J FETS such that each drain-source voltage Vds_(N) is approximately Vdrive(peak)/J.

10. The integrated circuit of claim 8, wherein each G_N has a capacitance Cg_N to a channel of the FET, and each gate coupling comprises a capacitance of about Cg_N/(N−

2) between G_N and S₁ for each N, 2<

N≦

J.

12. The integrated circuit of claim 8, further comprising a resistive divider for biasing a FET M_N, N>

1, of the FET stack.

14. A Class A, B or C RF PA comprising an integrated circuit according to claim 8, wherein the multiple-FET stack is configured as a primary amplifying device of the Class A, B or C RF PA.

15. A quad mixer comprising an integrated circuit according to claim 8.

16. A Class F RF PA comprising an integrated circuit according to claim 8, wherein the multiple-FET stack is configured as a primary amplifying device of the Class F RF PA.

11. An integrated circuit including a multiple-FET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref the integrated circuit comprising:

a) a series stack of J same-polarity FETs M_N, N an integer between 1 and J and J an integer 3 or greater, each FET M_N having a source S_N, a gate G_N and a drain D_N,

b) an input signal node coupled to the gate G₁ of a signal-input FET M₁ of the FET stack;

c) for 0<

N<

J, a series coupling between each drain D_N and the source S_(N+1) of a next higher FET M_(N+1) of the FET stack;

d) for 1<

N≦

J, a gate coupling between each gate G_N and at least one lower FET M<sub>(N−

K)</sub>, K an integer between 1 and (N−

1), in a configuration enslaving each FET M_(N+1) to M₁ so as to conduct substantially concurrently with, and under control of, conduction in M₁;

e) a source coupling for the FET stack between S₁ and Vref; and

f) a drain coupling for the FET stack between D_J and Vdrive;

wherein

g) a gate coupling circuit for a FET M_N, 2<

N≦

J, comprises a zener diode.

13. An integrated circuit including a multiple-FET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref, the integrated circuit comprising:

a) a series stack of J same-polarity FETs M_N, N an integer between 1 and J and J an integer 3 or greater, each FET M_N having a source S_N, a gate G_N and a drain D_N,

b) an input signal node coupled to the gate G₁ of a signal-input FET M₁ of the FET stack;

c) for 0<

N<

J, a series coupling between each drain D_N and the source S_(N+1) of a next higher FET M_(N+1) of the FET stack;

d) for 1<

N≦

J, a gate coupling between each gate G_N and at least one lower FET M<sub>(N−

K)</sub>, K an integer between 1 and (N−

1), in a configuration enslaving each FET M_(N+1) to M₁ so as to conduct substantially concurrently with, and under control of, conduction in M₁;

e) a source coupling for the FET stack between S₁ and Vref;

f) a drain coupling for the FET stack between D_J and Vdrive; and

g) a diode configured in a charge-pump circuit for biasing a FET M_N, N>

1, of the FET stack.

17. An RF power amplifier (PA) circuit configured for operation at a center frequency F₀, the PA circuit integrated onto a monolithic substrate and comprising:

a) a stack of J FETs M_N, for each integer value of N between 1and J, J an integer greater than one, each FET M_N having a source S_N, a gate G_N and a drain D_N, the stack configured to control an output signal Vdrive with respect to a reference voltage Vref at a characteristic impedance of Zdrive, the FET stack including

i) an input signal node coupled to the gate G₁ of a lowest FET M₁,

ii) channel couplings from the source S_N of each FET M_N, for N>

1, to the drain D<sub>(N−

1)</sub> of a next lower FET M<sub>(M−

1)</sub>,

iii) gate couplings from D_N of each FET M_N;

for N>

1, to a lower FET so as to cause M_N to conduct substantially concurrently with M₁,

iv) a FET stack reference coupling between S₁ and Vref, and

v) a FET stack output coupling between D_j and Vdrive; and

b) a shunt filter circuit configured to effect a shunt path between Vref and Vdrive having a local minimum impedance at approximately a harmonic frequency of F₀.

18. The PA of claim 17, wherein the FET stack a) is configured to control Vdrive at a characteristic impedance of Zdrive, and wherein the local minimum impedance of the shunt filter circuit is approximately a complex conjugate of Zdrive.

19. A wireless transmitter comprising a PA according to claim 18, further comprising an antenna having a characteristic impedance Zant coupled to the PA via an impedance matching filter.

20. The PA of claim 17, the shunt filter circuit b) is configured to have a first local minimum impedance at a first shunt frequency F_SH1 approximately equal to 2·

F₀, and a second local minimum impedance at a second shunt frequency F_SH2 approximately equal to 3·

F₀.

21. The PA of claim 19, wherein the FET stack a) is configured to control Vdrive at a characteristic impedance of Zdrive, and wherein the first and second local minimum impedances of the shunt filter are both approximately matched to Zdrive.

22. The PA of claim 17, wherein the shunt filter circuit b) further comprises a controllable device for changing the frequency of the local minimum impedance to accommodate changes in the operating center frequency F₀.

23. The PA of claim 17, wherein the local minimum impedance of the shunt filter circuit includes a non-zero and substantially resistive component.

24. The PA of claim 23, wherein the local minimum impedance of the shunt filter circuit includes a non-zero and substantially resistive component. No imaginary component.

25. An integrated RF Power Amplifier (PA) circuit, comprising:

a) an input node to accept an input signal with respect to a first reference voltage Vref1, coupled to a gate G1 of a first FET M1 having a first polarity;

b) a plurality of additional FETs M2 to Mn having the same polarity as M1 and coupled in series with M1 to form a control circuit configured to control conduction between the reference voltage and an output drive node, wherein FETs M2 to Mn are each enslaved to M1;

c) a FET −

M1 having opposite polarity than FET M1, having a channel coupled to a second supply voltage reference Vref2 different from Vref1, and having a gate coupled to the input signal without phase inversion; and

d) a plurality of additional FETs −

M2 to −

Mn having the same polarity as FET −

M1 and coupled in series with −

M1 to form a control circuit configured to control conduction between the second supply voltage reference Vref2 and the output drive node, wherein FETs −

M2 to −

Mn are each enslaved to −

M1.

26. The PA of claim 25, wherein each gate of FETs M2 to Mn is capacitively decoupled to another of the FETs in series therewith, and each gate of FETs −

M2 to −

Mn is capacitively decoupled to another of the FETs in series therewith.

27. The PA of claim 26, wherein each gate of FETs M2 to Mn is capacitively decoupled to Vref1, and each gate of FETs −

M2 to −

Mn is capacitively decoupled to Vref2.