Semiconductor memory device

• US 7,248,495 B2
• Filed: 04/05/2006
• Issued: 07/24/2007
• Est. Priority Date: 05/21/2001
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Arimoto, Kazutami, Shimano, Hiroki
• Primary Examiner(s): Yoha; Connie C.
• Application Number:
  US11/397,811
• Publication Number:
  US 20060193164A1
• Time in Patent Office: 475 Days
• Field of Search: 365/149, 365/189.09, 365/233, 365/230.01, 257/301, 257/302
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2211/4013 Memory devices with multiple cells per bit, e.g. twin-cells
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor

Abstract

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Claims

1. A semiconductor memory device, comprising:

a plurality of memory cells arranged in rows and columns, each of said memory cells including a capacitor including a cell plate electrode and a storage electrode arranged facing to said cell plate electrode, for accumulating electric charges corresponding to storage data, each memory cell being electrically isolated from adjacent memory cells thereto by means of a trench insulating film formed in a bottom of a cell isolating region of a trench structure, and each cell plate electrode comprising (i) a first electrode layer formed at least on a side wall of the trench and (ii) a second electrode layer formed above said trench insulating film and electrically connected to the first electrode layer formed on said side wall, said storage electrode being formed at a surface of a semiconductor region and facing to said cell plate electrode with a capacitor insulating film laid in between and being isolated from the storage electrode of an adjacent memory cell by means of the trench insulating film, and the trench being formed in said semiconductor region;

a plurality of word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells in a corresponding row, said word lines being formed in a same interconnection layer as the cell plate electrodes;

a plurality of bit lines arranged corresponding to the columns of memory cells and each connecting to the memory cells on a corresponding column, the bit lines being arranged in pairs; and

row selecting circuitry for selecting an addressed word line out of the word lines in accordance with an address signal, the memory cells being arranged such that data in selected memory cells on an addressed row are simultaneously read out onto bit lines in a pair by a selected word line.

2. The semiconductor memory device according to claim 1, wherein the cell plate electrode is arranged, commonly to the memory cells arranged in two rows, extending in a row direction.

3. A semiconductor memory device, comprising:

a plurality of memory cells arranged in rows and columns, each of said memory cells including a capacitor including a cell plate electrode and a storage electrode arranged facing to said cell plate electrode, for accumulating electric charges corresponding to storage data, each memory cell being electrically isolated from adjacent memory cells thereto by means of a trench insulating film formed in a bottom of a cell isolating region of a trench structure, and each cell plate electrode comprising an electrode layer formed, at least on a side wall of the trench, (1) being electrically isolated from the electrode layer formed on another side wall opposite in a column direction of the trench by means of said trench isolating film, and (2) extending in a row direction, said storage electrode being formed at a surface of a semiconductor region and facing to said cell plate electrode with a capacitor insulating film laid in between, and the trench being formed in said semiconductor region;

a plurality of word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells in a corresponding row, said word lines being formed in a same interconnection layer as the cell plate electrodes;

a plurality of bit lines arranged corresponding to the columns of memory cells and each connecting to the memory cells on a corresponding column, the bit lines being arranged in pairs; and

row selecting circuitry for selecting an addressed word line out of the word lines in accordance with an address signal, the memory cells being arranged such that data in selected memory cells on an addressed row are simultaneously read out onto bit lines in a pair by a selected word line.

4. The semiconductor memory device according to claim 3, wherein the cell plate electrode is separately arranged corresponding to each respective row of the memory cells.