Apparatus employing predictive failure analysis based on in-circuit FET on-resistance characteristics

• US 7,248,979 B2
• Filed: 05/09/2005
• Issued: 07/24/2007
• Est. Priority Date: 05/09/2005
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bandholz, Justin Potok
• Primary Examiner(s): Nghiem; Michael
• Application Number:
  US11/124,940
• Publication Number:
  US 20060265158A1
• Time in Patent Office: 806 Days
• Field of Search: 702/57, 702/64, 702/65
• US Class Current: 702/65
• CPC Class Codes: G06F 11/008 Reliability or availability analysis

Abstract

A computing system includes a semiconductor which sources/sinks current to/from components within the system, an in-circuit semiconductor on-resistance characterization circuit which measures the on-resistance of the semiconductor, and a processor which periodically or continuously engages the characterization circuit over the life of the semiconductor to obtain a series of on-resistance measurements. Depending on the type of semiconductor used, or depending on arbitrary design limitations, the computing system predicts semiconductor failure based on either a relative mode or an absolute mode. The relative mode is useful when using FET'"'"'s since on-resistance values vary significantly. In the relative mode, an optional NVRAM is used to store one or more on-resistance measurements which may serve as a reference for assuring proper circuit operation within tolerable deviations from the reference. In the absolute mode, one or more optional thresholds are utilized to assure that circuit operation remains in a known good region.

Claims

1. Apparatus comprising:

a processor having access to a non-volatile memory;

a semiconductor having a measurable on-resistance while sourcing/sinking current to/from components of the apparatus; and

a sensor which is coupled to said processor and said semiconductor and which measures the on-resistance of said semiconductor during normal operations of the apparatus;

wherein, the processor is effective to;

monitor the on-resistance of said semiconductor over a predetermined portion of the life of the semiconductor;

predict that the semiconductor is likely to fail based on the monitoring; and

report a predictive failure to the apparatus based on the prediction, wherein the prediction is made by comparing a recent on-resistance value to a stored on-resistance value and determining that the recent on-resistance value exceeds an allowable deviation from the stored on-resistance value which is stored in the non-volatile memory, wherein the recent, and stored, on-resistance values are produced by the monitoring.

2. Apparatus of claim 1 wherein the prediction is made by comparing a measured value, which is a function of the measured value of on-resistance, to a stored value which is stored in the non-volatile memory, the stored value being related to generic on-resistance characteristics.

3. Apparatus of claim 1 wherein the stored on-resistance value is the earliest value of on-resistance stored which corresponds to said semiconductor.

4. Apparatus of claim 1 wherein the reporting includes reporting a plurality of predictive failures based on a plurality of allowable deviations from the stored on-resistance value.

5. Apparatus of claim 4 wherein the plurality of predictive failures include a warning level reported in response to exceeding a first allowable deviation, and a shutdown level reported in response to exceeding a second allowable deviation which is greater than the first allowable deviation wherein the shutdown level is accompanied by a disablement of a circuit in the apparatus.

6. Apparatus of claim 1 wherein the prediction is made by comparing a recent on-resistance value to a predetermined threshold and determining that the recent on-resistance value exceeds the predetermined threshold, wherein the recent on-resistance value is produced by the monitoring.

7. Apparatus of claim 6 wherein the reporting includes reporting a plurality of predictive failures based on a plurality of predetermined thresholds.

8. Apparatus of claim 7 wherein the plurality of predictive failures include a warning level reported in response to exceeding a first threshold, and a shutdown level reported in response to exceeding a second threshold which is greater than the first threshold wherein the shutdown level is accompanied by a disablement of a circuit in the apparatus.

9. Apparatus of claim 1 wherein the predetermined portion of the life of the semiconductor corresponds to the time between the earliest installation of the semiconductor into the apparatus and the time which corresponds to the currently measured on-resistance value.

10. A method comprising:

monitoring the on-resistance of a semiconductor over a predetermined portion of the life of the semiconductor, wherein the semiconductor is a semiconductor which sources/sinks current to/from components of an apparatus and wherein the on-resistance is measured in-circuit during normal operations of the apparatus;

predicting that the semiconductor is likely to fail based on said monitoring; and

reporting a predictive failure to a user based on said prediction, wherein said prediction is made by comparing a recent on-resistance value to a stored on-resistance value and determining that the recent on-resistance value exceeds an allowable deviation from the stored on-resistance value, wherein the recent, and stored, on-resistance values are produced by said monitoring.

11. A method of claim 10 wherein the stored on-resistance value is the earliest value of on-resistance stored which corresponds to the semiconductor.

12. A method of claim 10 wherein said reporting includes reporting a plurality of predictive failures based on a plurality of allowable deviations from the stored on-resistance value.

13. A method of claim 12 wherein the plurality of predictive failures include a warning level reported in response to exceeding a first allowable deviation, and a shutdown level reported in response to exceeding a second allowable deviation which is greater than the first allowable deviation wherein the shutdown level is accompanied by a disablement of a circuit in the apparatus.

14. A method of claim 10 wherein said prediction is made by comparing a recent on-resistance value to a predetermined threshold and determining that the recent on-resistance value exceeds the predetermined threshold, wherein the recent on-resistance value is produced by said monitoring.

15. A method of claim 14 wherein said reporting includes reporting a plurality of predictive failures based on a plurality of predetermined thresholds.

16. A method of claim 15 wherein the plurality of predictive failures include a warning level reported in response to exceeding a first threshold, and a shutdown level reported in response to exceeding a second threshold which is greater than the first threshold wherein the shutdown level is accompanied by a disablement of a circuit in the apparatus.

17. A method of claim 10 wherein the predetermined portion of the life of the semiconductor corresponds to the time between the earliest installation of the semiconductor into the apparatus and the time which corresponds to the currently measured on-resistance value.