Generating unique identifiers in a computer system
First Claim
1. A method for creating a series of unique identifiers using a processor coupled to first memory and to at least one block of second memory slower than the first memory, the method comprising the steps of:
- storing a predetermined identifier in said second memory and in said first memory;
setting a bit string in said second memory to a first logical value;
setting a number subfield and a range subfield, together comprising an extension field in said first memory, to a second logical value; and
generating a monotonic sequence of said unique identifiers by repetitively performing the steps of;
incrementing said number subfield;
creating said unique identifier by concatenating said predetermined identifier and said extension field; and
when said number subfield contains all of the first logical value, performing the steps of;
setting to the second logical value, a next sequential bit in the bit string in said second memory;
incrementing said range subfield in said first memory; and
resetting said number subfield to the second logical value.
1 Assignment
0 Petitions
Accused Products
Abstract
Generating unique identifiers (UUIDs) for software objects and other components in a network in which a large number of components may exist simultaneously and/or over a period of time. UUIDs generated by a particular product are divided into two sub-fields. One sub-field is stored in non-volatile memory, and incremented infrequently. The other sub-field is stored in volatile memory, that can be incremented frequently. During operation, the product creating the UUIDs generates new UUIDs by incrementing the field stored in volatile memory. When overflow of the volatile memory field occurs, the field stored in non-volatile memory is incremented. A block of non-volatile memory is initialized to all of a first logical state, and the bits therein are then sequentially cleared to generate a subsequent unique identifier. The present system provides the equivalent of a counter that can count up to the number of available bits in non-volatile memory plus one, while reducing the number of non-volatile memory erase cycles to one cycle for each time all the bits are cleared.
25 Citations
11 Claims
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1. A method for creating a series of unique identifiers using a processor coupled to first memory and to at least one block of second memory slower than the first memory, the method comprising the steps of:
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storing a predetermined identifier in said second memory and in said first memory; setting a bit string in said second memory to a first logical value; setting a number subfield and a range subfield, together comprising an extension field in said first memory, to a second logical value; and generating a monotonic sequence of said unique identifiers by repetitively performing the steps of; incrementing said number subfield; creating said unique identifier by concatenating said predetermined identifier and said extension field; and when said number subfield contains all of the first logical value, performing the steps of; setting to the second logical value, a next sequential bit in the bit string in said second memory; incrementing said range subfield in said first memory; and resetting said number subfield to the second logical value. - View Dependent Claims (2, 3)
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4. A method for creating a series of unique identifiers using a processor coupled to first memory and to at least one block of second memory slower than the first memory, the method comprising the steps of:
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storing a predetermined identifier in said second memory and in said first memory; setting a bit string in said second memory to a value of all of a first logical value; setting a counter in said second memory to a value of a second logical value; setting a number subfield and a range subfield, together comprising an extension field in said first memory, to the second logical value; and generating a monotonic sequence of said unique identifiers by repetitively performing the steps of; incrementing said number subfield; creating said unique identifier concatenating said predetermined identifier and said extension field; and when said number subfield contains all of the first logical value, performing the steps of; incrementing said range subfield in said first memory; and resetting said number subfield to the second logical value; setting to second logical value, a next sequential bit in the bit string in said second memory; and when said bit string in said second memory contains all of the second logical value, performing the steps of; incrementing counter in said second memory; and resetting said bit string to all of the first logical value. - View Dependent Claims (5, 6)
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7. A system for generating a series of unique identifiers for use in a computer network, the system comprising:
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first memory containing one of the unique identifiers comprising a predetermined identifier and a field including a number subfield and a range subfield; second memory slower than the first memory containing a copy of wild predetermined identifier and bit string representing a value of said range subfield; and a processor coupled to said first memory and said second memory; wherein said system generates a monotonic sequence of said unique identifiers by incrementing said number subfield; wherein, when said number subfield contains all of a first logical value, a hit in the bit string in said second memory is set to a second logical value;
said range subfield is incremented; and
said number subfield is reset to the second logical value; andwherein, a value for said one of the unique identifiers is determined by storing, in said range subfield, the binary equivalent of the number of the second logical value bits in the bit string in said second memory. - View Dependent Claims (8)
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9. A system for generating a series of unique identifiers for use in a computer network, the system comprising:
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first memory containing one of the unique identifiers comprising a predetermined identifier and a field including a number subfield and a range subfield; second memory slower than the first memory containing a counter, a copy of said predetermined identifier and bit string representing a value of said range subfield; and a processor coupled to said first memory and said second memory; wherein said system generates a monotonic sequence of said unique identifiers by incrementing said number subfield; wherein, when said number subfield contains all of a first logical value, a bit in the bit string in said second memory is set to a second logical value;
said range subfield is incremented; and
said number subfield is reset to the second logical value; andwherein, when said bit string in said second memory contains all of the second logical value, the counter in said second memory is incremented and the bit string in said second memory is set to all of the first logical value. - View Dependent Claims (10, 11)
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Specification