Programmatic time-gap defect detection apparatus and method

• US 7,249,203 B2
• Filed: 11/17/2003
• Issued: 07/24/2007
• Est. Priority Date: 10/09/2001
• Status: Expired due to Term

• Current Assignee: Toshiba Client Solutions CO., Ltd. (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Aftg-Tg Lcc
• Inventors: Adams, Phillip M.
• Primary Examiner(s): Huynh; Kim
• Assistant Examiner(s): Hassan; Aurangzeb
• Application Number:
  US10/715,340
• Publication Number:
  US 20040153797A1
• Time in Patent Office: 1,345 Days
• Field of Search: 714/815, 710/25
• US Class Current: 710/25
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24

Abstract

Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user.

Claims

1. An apparatus for detecting time-gap defects in a computer system having devices interconnected to one another, the apparatus comprising:

a memory device to store data structures comprising executables and operational data;

a processor operably connected to the memory device to process the data structures;

a controller to control an exchange of data between the devices and to detect errors in the exchange; and

the memory device, wherein the data structures further comprise a detection module, executable by the processor and comprising;

an operation module to initiate an exchange of data producing a data stream between at least two of the devices;

a delay module to dynamically assign a value to a delay to be introduced into the data stream, and

a verification module to determine whether an error occurred as a result of the delay and remained undetected by the controller.

2. The apparatus of claim 1, wherein the detection module is further programmed to receive an input for controlling the dynamic assignment of the value of the delay.

3. The apparatus of claim 1, wherein the detection module is programmed to select the value iteratively.

4. The apparatus of claim 3, wherein the detection module is programmed to iteratively select by a marching method over a time domain.

5. The apparatus of claim 4, wherein the marching method comprises selecting an initial value and an increment and stepping across at least a portion of the time domain by adding the increment to the value to select a new value.

6. The apparatus of claim 3, wherein iteratively selecting comprises dynamically bracketing the value of the delay above which time gap errors occur and remain undetected by the controller.

7. The apparatus of claim 1, wherein the detection module is programmed to dynamically bracket the value of the delay below which time gap errors do not occur and remain undetected by the controller.

8. The apparatus of claim 1, wherein the detection module is programmed to iteratively select the value of the delay above which time gap errors occur.

9. The apparatus of claim 1, wherein the detection module is programmed to iteratively select the value of the delay below which time gap errors do not occur.

10. An article including a computer readable medium storing executable modules comprising:

a control module to control an exchange of data between devices in a computer system, and to detect errors occurring in the exchange;

a detection module, executable to detect errors occurring due to a time gap and remaining undetected by the computer system, the detection module comprising;

an operation module to initiate an exchange of data producing a data stream between at least two of the devices;

a delay module to dynamically assign a value of a delay time to be introduced into the data stream; and

a verification module to determine whether an error occurred due to the delay time in the data stream and remained undetected to the computer system.

11. The article of claim 10, wherein the detection module is programmed to iteratively bracket a first value of the delay time, above which time gap errors occur and remain undetected by the control module, and a second value of the delay time, below which time gap errors do not occur and remain undetected by the control module.

12. A method for detecting time-gap defects in components of a computer system, the method comprising:

providing a detection module to execute on a processor to initiate, detect, and verify reporting of errors after a check therefor by the computer system, that remain undetected to the computer system due to time gaps introduced into data streams communicated between devices in the computer system;

loading the detection module onto a computer system comprising a processor, a memory, devices connected to exchange data with one another, and controllers for controlling the exchange of data therebetween; and

executing the detection module by the processor to detect errors occurring and remaining otherwise undetected by the computer system due to the time gaps.

13. The method of claim 12, wherein executing the detection module further comprises:

initiating an exchange of data producing a data stream between the devices in the computer system;

introducing a controlled delay in the data stream;

checking the data for errors precipitated by the controlled delay; and

identifying devices incurring errors that remain undetected by the computer system.

14. The method of claim 12, further comprising receiving operating parameters to adjust the controlled delay to precipitate the errors.

15. The method of claim 12, further comprising iteratively selecting the value of the controlled delay.

16. The method of claim 12, further comprising iteratively selecting the value of the controlled delay by a marching method over a time domain.