Bus access arbitration scheme
First Claim
1. A processing system, comprising:
- a bus;
a plurality of processors coupled to the bus; and
a bus arbiter configured to assign a second tier weight to one or more of the processors, and sequentially grant bus access to the one or more processors having a second tier weight during an initial portion of a bus interval based on the assigned second tier weights, the bus arbiter being further configured to grant bus access to any one of the processors during the initial portion of the bus interval in response to a first tier request from said any one of the processors having a first tier weight, for each of the one or more of the processors granted access during the initial portion of the bus interval, the tier weight associated with a corresponding tier request is reduced for each time slot within the initial portion of the bus interval a processor has been granted access, the bus arbiter being further configured to reset the first tier weight of the one or more processors at the beginning of a quality of service interval wherein the length of the quality of service interval is not equal to the length of the bus interval.
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Abstract
A bus arbitration scheme in a processing system. The processing system includes a bus, a plurality of processors coupled to the bus, and a bus arbiter. The bus arbiter may assign a first tier weight to each of the processors in a first tier, and a second tier weight to each of the processors in a second tier. The bus arbiter may sequentially grant bus access to the one or more processors during an initial portion of a bus interval based on the assigned second tier weights, and grant bus access to any one of the processors during the initial portion of the bus interval in response to a request from said any one of the processors having a first tier weight. When multiple processors are requesting access to the bus, the bus arbiter may grant bus access to the requesting processor with the highest weight in the highest tier.
75 Citations
34 Claims
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1. A processing system, comprising:
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a bus; a plurality of processors coupled to the bus; and a bus arbiter configured to assign a second tier weight to one or more of the processors, and sequentially grant bus access to the one or more processors having a second tier weight during an initial portion of a bus interval based on the assigned second tier weights, the bus arbiter being further configured to grant bus access to any one of the processors during the initial portion of the bus interval in response to a first tier request from said any one of the processors having a first tier weight, for each of the one or more of the processors granted access during the initial portion of the bus interval, the tier weight associated with a corresponding tier request is reduced for each time slot within the initial portion of the bus interval a processor has been granted access, the bus arbiter being further configured to reset the first tier weight of the one or more processors at the beginning of a quality of service interval wherein the length of the quality of service interval is not equal to the length of the bus interval. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A processing system, comprising:
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a bus; a plurality of processors coupled to the bus; and a bus arbiter configured to assign a first tier weight to each of the processors in a first tier, and assign a second tier weight to each of the processors in a second tier, the bus arbiter being further configured to arbitrate between one or more of the processors requesting access to the bus by granting bus access to the requesting processor with the highest weight in the highest tier during an initial portion of a bus interval, the first tier being higher than the second tier, for each of the one or more of the processors granted access during the initial portion of the bus interval, the tier weight associated with a corresponding tier request is reduced for each time slot within the initial portion of the bus interval a processor has been granted access, the bus arbiter being further configured to reset the first tier weight of the one or more processors at the beginning of a quality of service interval wherein the length of the quality of service interval is not equal to the length of the bus interval. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method of arbitrating between a plurality of processors requesting access to a bus, comprising:
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assigning a second tier weight to each of one or more of the processors; sequentially granting bus access to the one or more processors during an initial portion of a bus interval based on the assigned second tier weights; granting bus access to any one of the processors during the initial portion of the bus interval in response to a request from said any one of the processors having a first tier weight; reducing the first tier weight for each of the one or more of the processors granted access during the initial portion of the bus interval; and resetting the first tier weight of the one or more processors at the beginning of the quality of service interval wherein the length of the quality of service interval is not equal to the length of the bus interval. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. A method of arbitrating between a plurality of processors requesting access to a bus, comprising:
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assigning a first tier weight to each of the processors in a first tier; assigning a second tier weight to each of the processors in a second tier; arbitrating between one or more of the processors requesting access to the bus by granting bus access to the requesting processor with the highest weight in the highest tier, the first tier being higher than the second tier; reducing the first tier weight for each of the one or more of the processors granted access during the initial portion of the bus interval; and resetting the first tier weight of the one or more processors at the beginning of the quality of service interval wherein the length of the quality of service interval is not equal to the length of the bus interval. - View Dependent Claims (29, 30, 31, 32, 33, 34)
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Specification