Method and system for controlling memory accesses to memory modules having a memory hub architecture

• US 7,249,236 B2
• Filed: 10/12/2004
• Issued: 07/24/2007
• Est. Priority Date: 08/29/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., Lee, Terry R.
• Primary Examiner(s): Peugh; Brian R.
• Application Number:
  US10/963,824
• Publication Number:
  US 20050066137A1
• Time in Patent Office: 1,015 Days
• Field of Search: 711167-169, 711/105, 711/154, 710 52- 57
• US Class Current: 711/169
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1673 using buffers

Abstract

A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Claims

1. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a memory request queue storing a least one memory request received through an input port, the memory request queue being coupled to the memory devices to transmit each memory request stored in the memory request queue to the memory devices, the memory request queue being operable to output a respective read released signal identifying each read memory request transmitted to the memory devices and to output a respective write released signal identifying each write memory request transmitted to the memory devices;

a flow control unit coupled to the memory request queue, the flow control unit being operable to receive the read released signal and the write released signal from the memory request queue, the flow control unit being operable to output read status signals corresponding to the read released signals and write status signals corresponding to the write released signals;

a memory read queue coupled to the memory devices, the memory read queue receiving read data from the memory devices and storing the read data for coupling to an output port; and

a response generator coupled to the flow control unit and the memory read queue, the response generator being operable to generate and transmit from an output port read responses each containing the read data from the read data queue and a read status signal corresponding to a status signal from the flow control unit, the response generator further being operable to transmit from the output port write responses each containing a write status signal corresponding to a status signal from the flow control unit.

2. The memory module of claim 1 wherein the memory devices comprises respective dynamic random access memory devices.

3. The memory module of claim 1 wherein the input port of the memory request queue in the memory hub and the output port of the response generator in the memory hub comprises optical input and output ports, respectively.

4. The memory module of claim 1 wherein the memory request queue is operable to simultaneously store both read memory requests and write memory requests.

5. The memory module of claim 1 wherein the read released signal is coupled to the flow control unit responsive to the memory request queue transmitting each read request to the memory devices, and wherein the write released signal is coupled to the flow control unit responsive to the memory request queue transmitting each write request to the memory devices.

6. The memory module of claim 5 wherein the flow control unit is operable to output a respective one of the read status signal corresponding to each read released signal, each of the read status signals uniquely identifying a respective read request, and wherein the flow control unit is operable to output a respective one of the write status signals corresponding to each of the write released signals, each write status signal uniquely identifying a respective write request.

7. The memory module of claim 1 wherein the response generator is operable to generate and transmit from an output port a read response signal containing either read data and one of the read status signals or read data, one of the read status signals and one of the write status signals.

8. The memory module of claim 7 wherein the response generator is further operable to generate and transmit from an output port a write response signal containing the write status signal without the read data.

9. A memory system comprising:

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices;

a memory request queue storing at least memory one request received through an input port, the memory request queue being coupled to the memory devices to transmit each memory request stored in the memory request queue to the memory devices, the memory request queue being operable to output a respective read released signal identifying each read memory request transmitted to the memory devices and to output a respective write released signal identifying each write memory request transmitted to the memory devices;

a flow control unit coupled to the memory request queue, the flow control unit being operable to receive the read released signal and the write released signal from the memory request queue, the flow control unit being operable to output read status signals corresponding to the read released signals and write status signals corresponding to the write released signals;

a memory read queue coupled to the memory devices, the memory read queue receiving read data from the memory devices and storing the read data for coupling to an output port; and

a response generator coupled to the flow control unit and the memory read queue, the response generator being operable to generate and transmit from an output port read responses each containing the read data from the read data queue and a corresponding one of the read status signals from the flow control unit, the response generator further being operable to transmit from the output port write responses each containing one of the write status signals from the flow control unit; and

a memory hub controller comprising;

a memory request queue storing at least one memory request received through an input port, the memory request queue being coupled to the memory request queue of each of the memory modules to transmit each memory request stored in the memory request queue to at least one of the memory modules responsive to a flow control signal;

a response queue coupled to the response generator in each of the memory modules, the response queue being coupled to receive the read responses and the write responses from the response generators in the memory modules, the response queue being operable to couple at least the read data from each of the read responses to a data output port and to couple the read status signal from each read response and the write status signal from each write response to a flow control port; and

a flow control unit coupled to receive the read status signals and the write status signals from the response queue of the memory hub controller, the flow control unit being operable to determine from the status signals the number of outstanding memory requests in each of the memory modules and to generate and couple to the memory request queue of the memory hub controller a flow control signal indicating that additional memory requests can be sent to each of the memory modules based on the number of outstanding memory requests in each of the memory modules.

10. The memory system of claim 9 wherein the memory devices comprises respective dynamic random access memory devices.

11. The memory system of claim 9 wherein the input port of the memory response queue in the memory hub controller and the input port of each memory request queue in the memory modules comprise respective optical input ports, and wherein the output port of the memory request queue in the memory hub controller and the output port of each memory response generator in the memory modules comprise respective optical output ports.

12. The memory system of claim 9 wherein the memory request queues in the memory hub controller and in each of the memory modules are operable to simultaneously store both read memory requests and write memory requests.

13. The memory system of claim 9 wherein the read released signal is coupled to the flow control unit in each memory module responsive to the memory request queue in the memory module transmitting each read request to the memory devices in the memory module, and wherein the write released signal is coupled to the flow control unit in each memory module responsive to the memory request queue in the memory module transmitting each write request to the memory devices in the memory module.

14. The memory system of claim 13 wherein the flow control unit in each memory module is operable to output a respective one of the read status signals corresponding to each read released signal, each read status signal uniquely identifying a respective read request, and wherein the flow control unit in each memory module is operable to output a respective one of the write status signals corresponding to each write released signal, each write status signal uniquely identifying a respective write request.

15. The memory system of claim 9 wherein the response generator in each memory module is operable to generate and transmit from an output port a read response containing either read data and one of the read status signals or read data, one of the read status signals and one of the write status signals.

16. memory system of claim 15 wherein the response generator is further operable to generate and transmit from an output port a write response containing one of the write status signals without the read data.

17. The memory system of claim 9 wherein the memory request queue in the memory hub controller is further operable to issue from the output port along with each memory request a request identification uniquely identifying the respective memory request.

18. The memory system of claim 9 wherein the flow control unit in the memory hub controller is operable to generate and couple to the memory request queue the request identification for each memory request.

19. The memory system of claim 18 wherein the flow control unit in the memory hub controller is further operable to generate the flow control signal on the basis of a comparison between the request identification coupled to the memory request queue and the read status signals and the write status signals received from the response queue.

20. A processor-based system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a memory hub controller storing a plurality of memory requests and outputting each stored memory request responsive to a flow control signal generated as a function of received memory request status signals, the memory hub controller further receiving and storing read data and the memory request status signals, the memory hub controller outputting the stored read data; and

a plurality of memory modules coupled to the memory hub controller, each of the memory modules comprising;

a plurality of memory devices; and

a memory hub coupled to receive memory requests from the memory hub controller, the memory hub storing the memory requests received from the memory hub controller and coupling memory request signals corresponding to the stored memory requests to the memory devices in the memory module, the memory hub being operable to receive read data from the memory devices and to couple the read data to the memory hub controller, the memory hub further being operable to couple to the memory hub controller the memory request status signals, the memory request status signals identifying the memory requests that have been serviced by the memory devices coupled to the memory hub.

21. The processor-based system of claim 20 wherein the memory requests stored in and output from the memory hub controller comprise read memory requests and write memory requests.

22. The processor-based system of claim 20 wherein the memory hub controller comprises a memory request queue storing the memory requests and outputting the memory requests from the memory request queue responsive to the flow control signals.

23. The processor-based system of claim 20 wherein the memory hub controller is further operable to output with each memory request a request identifier that uniquely identifies the respective memory request.

24. The processor-based system of claim 23 wherein the memory hub controller is operable to generate the flow control signal by comparing the received memory request status signals to the request identifier.

25. The processor-based system of claim 24 wherein the memory hub is operable to generate the memory request status signals from the request identifier received from the memory hub controller.

26. A processor-based system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices;

a memory request queue storing at least memory one request received through an input port, the memory request queue being coupled to the memory devices to transmit each memory request stored in the memory request queue to the memory devices, the memory request queue being operable to output a respective read released signal identifying a read memory request transmitted to the memory devices and to output a respective write released signal identifying a write memory request transmitted to the memory devices;

a flow control unit coupled to the memory request queue, the flow control unit being operable to receive the read released signal and the write released signal from the memory request queue, the flow control unit being operable to output read status signals corresponding to the read released signals and write status signals corresponding to the write released signals;

a memory read queue coupled to the memory devices, the memory read queue receiving read data from the memory devices and storing the read data for coupling to an output port; and

a response generator coupled to the flow control unit and the memory read queue, the response generator being operable to generate and transmit from an output port read responses each containing the read data from the read data queue and a read status signal corresponding to one of the read status signals from the flow control unit, the response generator further being operable to transmit from the output port write responses each containing a write status signal corresponding to one of the write status signals from the flow control unit; and

a memory hub controller comprising;

a memory request queue storing at least one memory request received through an input port, the memory request queue being coupled to the memory request queue of each of the memory modules to transmit each memory request stored in the memory request queue to at least one of the memory modules responsive to a flow control signal;

a response queue coupled to the response generator in each of the memory modules, the response queue being coupled to receive the read responses and the write responses from the response generators in the memory modules, the response queue being operable to couple at least the read data from each read response to a data output port and to couple the read status signal from each read response and the write status signal from each write response to a flow control port; and

a flow control unit coupled to receive the read status signals and the write status signals from the response queue of the memory hub controller, the flow control unit being operable to determine from the status signals the number of outstanding memory requests in each of the memory modules and to generate and couple to the memory request queue of the memory hub controller a flow control signal indicating that additional memory requests can be sent to each of the memory modules based on the number of outstanding memory requests in each of the memory modules.

27. The processor-based system of claim 26 wherein the memory devices comprises respective dynamic random access memory devices.

28. The processor-based system of claim 26 wherein the input port of the memory response queue in the memory hub controller and the input port of each memory request queue in the memory modules comprise respective optical input ports, and wherein the output port of the memory request queue in the memory hub controller and the output port of each memory response generator in the memory modules comprise respective optical output ports.

29. The processor-based system of claim 26 wherein the memory request queues in the memory hub controller and in each of the memory modules are operable to simultaneously store both read memory requests and write memory requests.

30. The processor-based system of claim 26 wherein the read released signal is coupled to the flow control unit in each memory module responsive to the memory request queue in the memory module transmitting each read request to the memory devices in the memory module, and wherein the write released signal is coupled to the flow control unit in each memory module responsive to the memory request queue in the memory module transmitting each write request to the memory devices in the memory module.

31. The processor-based system of claim 30 wherein the flow control unit in each memory module is operable to output a read status signal corresponding to each read released signal, each read status signal uniquely identifying a respective read request, and wherein the flow control unit in each memory module is operable to output a write status signal corresponding to each write released signal, each write status signal uniquely identifying a respective write request.

32. The processor-based system of claim 26 wherein the memory request queue in the memory hub controller is further operable to issue from the output port along with each memory request a request identification uniquely identifying the respective memory request.

33. The processor-based system of claim 26 wherein the flow control unit in the memory hub controller is operable to generate and couple to the memory request queue the request identification for each memory request.

34. The processor-based system of claim 33 wherein the flow control unit in the memory hub controller is further operable to generate the flow control signal on the basis of a comparison between the request identification coupled to the memory request queue and the read status signals and the write status signals received from the response queue.

35. A method of reading data from and writing to a plurality of memory modules, comprising:

transmitting a plurality of memory request to the memory modules;

receiving each of the transmitted memory requests at the memory modules;

servicing the received memory requests in one of the memory modules at a rate that may differ from the rate at which the memory requests are transmitted to the memory module;

determining the number of memory requests that have been transmitted to the memory modules but not yet serviced by one of the memory modules; and

transmitting additional memory request to the memory modules as a function of the determination made as to the number of transmitted memory requests that have not yet been serviced by the memory module.

36. The method of claim 35 wherein the act of transmitting a plurality of memory request to the memory modules comprises transmitting either a write request or a read request to the memory modules along with a request identifier the uniquely identifies the write request or read request.

37. The method of claim 36 wherein the act of determining the number of memory requests that have been transmitted to the memory module but not yet serviced by the memory module comprises:

receiving from the memory module a memory request status signal that identifies the read requests and write requests that have been serviced; and

comparing the memory request status signals to the request identifiers.

38. In a computer system having a memory hub controller coupled to a plurality of memory modules each of which includes a plurality of memory devices, a method of accessing the memory modules using the memory hub controller, comprising:

transmitting a plurality of memory request from the memory hub controller to at least one of the memory modules;

storing the transmitted memory requests in the memory module to which the memory requests are transmitted;

accessing the memory devices in the memory module in accordance with the memory requests, the memory devices being accessed at a rate that may differ from the rate at which the memory requests are transmitted to the memory modules;

generating in each of the memory modules memory request status signals that identify which memory requests have been serviced in the memory module;

coupling the memory request status signals to the memory hub controller; and

transmitting additional memory requests from the memory hub controller to the memory modules as a function of the memory request status signals coupled to the memory hub controller.

39. The method of claim 38 wherein the act of transmitting a plurality of memory request from the memory hub controller to at least one of the memory modules comprises transmitting either a write request or a read request from the memory hub controller to at least one of the memory modules.

40. The method of claim 38 wherein the memory devices comprise random access memory devices.

41. The method of claim 38 wherein the act of transmitting a plurality of memory request from the memory hub controller to at least one of the memory modules comprises transmitting with each memory request a respective request identifier the uniquely identifies the memory request.

42. The method of claim 41 wherein the act of generating the memory request status signals comprises generating the memory request status signals in the memory modules from the request identifiers transmitted to the memory modules.

43. The method of claim 41 further comprising storing in the memory controller each request identifier transmitted to the memory modules, and wherein the act of transmitting additional memory requests from the memory hub controller as a function of the memory request status signals comprises comparing in the memory hub controller the memory request status signals to the request identifiers stored in the memory hub controller.