Control method for data transfer control unit
First Claim
1. A control method for controlling data transfer by a control unit for controlling the operation of an upper-level host itself so that said control unit reads data of predetermined capacity from a device into a buffer memory of a host controller equipped in said upper-level host, and accepts an interruption issued from said device after said device transfers the data of predetermined capacity to said host controller, said control method comprising:
- a data reading restricted step of said host controller reading the data from said device into said buffer memory for a unit amount with a part of the data of predetermined capacity left in said device;
a data transfer step of said control unit reading the data of said unit amount temporarily held in said buffer memory;
a buffer memory capacity detecting step of said host controller detecting whether or not said buffer memory is empty in parallel with said data transfer step; and
a residual data reading step of said host controller reading the data corresponding to the part of data of said predetermined capacity from said device into said buffer memory when said buffer memory is empty at said buffer memory capacity detecting step.
2 Assignments
0 Petitions
Accused Products
Abstract
An upper-level host has a control unit and a host controller for controlling the operation of a device. The host controller includes a buffer memory that reads data from the device into the buffer memory. The control unit reads data from the buffer memory and handles interruptions from the device. Moreover, the host controller reads data for every unit amount from the device with a part of the data of predetermined capacity left in the device, and reads data corresponding to a part of the data of predetermined capacity from the device into the buffer memory if the buffer memory is empty as the data in the buffer memory is transferred to the control unit.
6 Citations
11 Claims
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1. A control method for controlling data transfer by a control unit for controlling the operation of an upper-level host itself so that said control unit reads data of predetermined capacity from a device into a buffer memory of a host controller equipped in said upper-level host, and accepts an interruption issued from said device after said device transfers the data of predetermined capacity to said host controller, said control method comprising:
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a data reading restricted step of said host controller reading the data from said device into said buffer memory for a unit amount with a part of the data of predetermined capacity left in said device; a data transfer step of said control unit reading the data of said unit amount temporarily held in said buffer memory; a buffer memory capacity detecting step of said host controller detecting whether or not said buffer memory is empty in parallel with said data transfer step; and a residual data reading step of said host controller reading the data corresponding to the part of data of said predetermined capacity from said device into said buffer memory when said buffer memory is empty at said buffer memory capacity detecting step. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A control method for controlling data transfer by a control unit for controlling the operation of an upper-level host itself so that said control unit reads data of predetermined capacity from a device into a buffer memory of a host controller equipped in said upper-level host, and said host controller writes a CRC value into said device, said CRC value being the error detection data in transferring the read data, and said control unit accepts an interruption issued from said device having received said CRC value, said control method comprising:
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a total data reading step of said host controller reading the data of said predetermined capacity from said device into said buffer memory; a data transfer step of said control unit reading a unit amount of the data of said predetermined capacity temporarily held in said buffer memory; a buffer memory capacity detecting step of said host controller detecting whether or not said buffer memory is empty in parallel with said data transfer step; and a CRC value writing step of said host controller writing a CRC value into said device when said buffer memory is empty at said buffer memory capacity detecting step. - View Dependent Claims (9, 10, 11)
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Specification
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- Resources
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Current AssigneeRenesas Electronics Corporation
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Original AssigneeNEC Electronics Corporation (Renesas Electronics Corporation)
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InventorsKusumi, Takeo
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Primary Examiner(s)Bataille; Pierre-Michel
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Application NumberUS10/386,779Publication NumberTime in Patent Office1,595 DaysField of Search711/154, 711/152, 711/166, 711/170, 710/56, 710/57, 710/59US Class Current711/170CPC Class CodesG06F 13/385 for adaptation of a particu...G06F 3/0613 in relation to throughputG06F 3/0656 Data buffering arrangementsG06F 3/0676 Magnetic disk device
