Common feature mode for microprocessors in a multiple microprocessor system

• US 7,249,247 B2
• Filed: 09/13/2004
• Issued: 07/24/2007
• Est. Priority Date: 04/11/2000
• Status: Expired due to Fees

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Williams, David W., See, Valerie R.
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US10/940,394
• Publication Number:
  US 20050033950A1
• Time in Patent Office: 1,044 Days
• Field of Search: 712/229, 714/12, 714/4, 714/7, 713/1, 713/100, 713/375
• US Class Current: 712/229
• CPC Class Codes: G06F 8/61 Installation
• CPC Class Codes: G06F 8/64 Retargetable
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A mechanism whereby a set of microprocessors may be set to a common mode in which the microprocessors utilize one or more features that are common to all microprocessors. The common mode facilitates proper multiprocessor operation and permits a fix (e.g., a microcode patch) to be applied to each of the microprocessors based on this common mode. More particularly, at system startup, firmware or software can detect whether microprocessors are set to run in different modes (e.g., steppings) in a multiprocessor system. If not, the microprocessors are allowed to run in their normal mode, such as by writing a particular value (e.g., zero) to a configuration register associated with each microprocessor. If features are mixed, a different value can be written, (e.g., one), which tells each microprocessor to revert to a common mode of operation for that family of microprocessors, such as corresponding to a common stepping and/or clock speed. A common set of microcode patches may be downloaded to the microprocessors. Alternatively, the various microprocessors may also be instructed to run in a particular mode that emulates a particular stepping, e.g., by writing into the configuration register or registers a number between one and M that corresponds to a common stepping among the microprocessors.

Claims

1. In a computing environment including a plurality of computing elements and an intermediary mechanism, each computing element including internal components configured for operation in one or more different operating modes, a method for adjusting an operating mode to improve interoperability between the computing elements, the method comprising:

the intermediary mechanism communicating with a first computing element to detect one or more available operating modes available to the first computing element;

the intermediary mechanism communicating with a second computing element to detect a current operating mode of the second computing element; and

the intermediary mechanism communicating with the first computing element to alter a setting in the internal components of the first computing element to utilize a design alteration of the first computing element, utilization of the design alteration causing the first computing element to operate in a corresponding available operating mode that improves interoperability between the first computing element and the current operating mode of the second computing element.

2. The method of claim 1 further comprising, changing a mode on at least one other computing element to improve interoperability with the current operating mode of the second computing element.

3. The method of claim 1 wherein altering a setting in the internal components of the first computing element comprises changing the first computing element to operate with another stepping.

4. The method of claim 1 wherein altering a setting in the internal components of first computing element comprises changing the first computing element to operate with another instruction set.

5. The method of claim 4 wherein altering a setting in the internal components of the first computing element comprises changing the first computing element to operate with another stepping.

6. The method of claim 1 wherein the first computing element comprises a central processing unit and the second computing element comprises a graphics processing unit.

7. The method of claim 1 wherein the first computing element comprises a digital signal processing unit.

8. The method of claim 1 wherein the first computing element comprises a programmable gate array.

9. The method of claim 1 further comprising changing a mode on the second computing element.

10. The method of claim 1 wherein altering a setting in the internal components of the first computing element comprises communicating a message to the first computing element over a network.

11. The method of claim 1 wherein altering a setting in the internal components of the first computing element comprises changing a processor that primarily handles input/output operations to a processor that primarily handles computational operations.

12. At least one computer-readable medium having computer-executable instructions which when executed perform the method of claim 1.

29. At least one computer-readable medium having computer-executable instructions which when executed perform the method of claim 1.

30. The method of claim 1 wherein the computing environment includes a computer network and the intermediary mechanism communicating with a first computing element to detect one or more available operating modes available to the first computing element comprises the intermediary mechanism exchanging network communication with a first computing element to detect one or more available operating modes available to the first computing element.

31. The method of claim 30 wherein the intermediary mechanism communicating with a second computing element to detect a current operating mode of the second computing element comprises the intermediary mechanism exchanging network communication with the second computing element to detect a current operating mode of the second computing element.

32. The method of claim 31 wherein the intermediary mechanism communicating with the first computing element to alter a setting in the internal components of the first computing element to utilize a design alteration of the first computing element comprises the intermediary mechanism exchanging network communication with the first computing element to alter a setting in the internal components of the first computing element to utilize a design alteration of first computing element.

13. In a computing environment, a system comprising:

a computer network;

a plurality of processors connected to the computer network, each processor having internal components configured for operation in one or more different operating modes; and

an intermediary mechanism connected to the computer network, the intermediary mechanism configured to determine through the exchange network communication with a first processor and a second processor common operating mode that is available to each of the first processor and second processor, the intermediary mechanism being further configured to alter settings of internal components of the first and second processors through network communication to cause the first and second processors to operate in the common operating mode.

14. The system of claim 13, wherein the intermediary mechanism writes information to at least one register.

15. The system of claim 13, wherein the intermediary mechanism comprises a web service.

16. The system of claim 13 further comprising at least one other computing element having a changeable mode caused to be changed by the intermediary mechanism to improve interoperation with the common operating mode of the first and second processors.

17. The system of claim 13 wherein the intermediary mechanism causes the first processor to operate with another stepping.

18. The system of claim 13 wherein the intermediary mechanism causes the first processor to operate with another instruction set.

19. The system of claim 18 wherein the intermediary mechanism causes the first processor to operate with another stepping.

20. The system of claim 13 wherein the first processor comprises a central processing unit and the second processor comprises a graphics processing unit.

21. The system of claim 13 wherein the first processor comprises a digital signal processing unit.

22. The system of claim 13 wherein the first processor comprises a programmable gate array.

23. The system of claim 13 wherein the intermediary mechanism causes a mode change to the second processor.

24. The system of claim 13 wherein the first processor is changed from a mode that primarily handles input/output operations to a mode that primarily handles computational operations.

25. In a computing environment including plurality of computing elements and an intermediary mechanism, each computing element including internal components configured for operation in one or more different operating modes, a method for adjusting the operating modes of the plurality of computing elements to improve interoperability between the computing elements, the method comprising:

the intermediary mechanism communicating with a first computing element to detect one or more operating modes available to the first computing element;

the intermediary mechanism communicating with a second computing element to detect one or more operating modes available to the second computing element; and

the intermediary mechanism communicating with the first and second computing elements to alter a setting in the internal components of at least one of the first computing element and the second computing element to utilize a corresponding design alteration, utilization of the design alteration to the corresponding computing element synchronizing the operating modes of the first computing element and the second computing element to enhance interoperability between the first computing element and second computing element.

26. The method of claim 25 wherein synchronizing the modes comprises changing an instruction set.

27. The method of claim 25 wherein the first computing element comprises a microprocessor, and wherein synchronizing the modes comprises causing the microprocessor to run with a different stepping.

28. The method of claim 25 wherein the first computing element communicates with the second computing element via a network.

33. The method of claim 25 wherein the computing environment includes a computer network and the intermediary mechanism communicating with a first computing element to detect one or more available operating modes available to the first computing element comprises the intermediary mechanism exchanging network communication with a first computing element to detect one or more available operating modes available to the first computing element.

34. The method of claim 33 wherein the intermediary mechanism communicating with a second computing element to detect one or more operating modes of the second computing element comprises the intermediary mechanism exchanging network communication with the second computing element to detect one or more operating modes of the second computing element.

35. The method of claim 34 wherein the intermediary mechanism communicating with the first and second computing elements to alter a setting in the internal components of at least one of the first computing element and the second computing element to utilize a corresponding design alteration comprises the intermediary mechanism exchanging network communication with the first and second computing elements to alter a setting in the internal components of at least one of the first computing element and the second computing element to utilize a corresponding design alteration.