Method and apparatus for dynamically allocating processors

• US 7,249,358 B2
• Filed: 01/07/2003
• Issued: 07/24/2007
• Est. Priority Date: 01/07/2003
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Haar, Allen P, Sandon, Peter A, Krumm, Barry W, Rohrer, Norman J, Kartschoke, Paul D, Emma, Philip G
• Primary Examiner(s): An; Meng-Al T.
• Assistant Examiner(s): Tang; Kenneth
• Application Number:
  US10/248,303
• Publication Number:
  US 20040133892A1
• Time in Patent Office: 1,659 Days
• Field of Search: 718104-105, 712/220, 714/1
• US Class Current: 718/105
• CPC Class Codes: G06F 11/1497 Details of time redundant execution on a single processing unit
• CPC Class Codes: G06F 11/1637 using additional compare functionality in one or some but not all of the redundant processing components
• CPC Class Codes: G06F 11/182 based on mutual exchange of the output between redundant processing components
• CPC Class Codes: G06F 11/184 where the redundant components implement processing functionality
• CPC Class Codes: G06F 2201/845 Systems in which the redundancy can be transformed in increased performance
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

A computer system having a plurality of processors where each of the processors is dynamically assigned for execution of tasks based upon either performance or reliability.

Claims

1. A computer system comprising:

a plurality of processors adapted to execute instructions based on a performance metric or a reliability metric; and

an instruction control unit to receive instructions and to dynamically assign each one of the instructions to the plurality of processors for redundant execution by at least two of the processors according to the reliability metric, and dynamically assigns each one of the remaining received instructions for execution to each one of the remaining processors according to the performance metric, wherein the results of the redundant execution of the instruction according to the reliability metric are different from one another, and the instruction control unit assigns another one of the processors to execute the received instruction.

2. The computer system of claim 1 wherein the instruction control unit dynamically assigns each one of the received instructions to at least two of the processors for execution based upon the reliability metric.

3. The computer system according to claim 1, wherein the reliability metric comprises executing an instruction on a first processor and executing the same instruction on a second processor, comparing the results and reporting any differences in the results.

4. The computer system of claim 1, wherein the instructions comprise executable micro code instructions.

5. The computer system according to claim 1, wherein the reliability metric comprises employing a triple modular redundancy scheme with a voting mechanism to compare results and identify processing errors.

6. The computer system according to claim 5, wherein the voting mechanism further comprises a checksum comparison to determine a final result of the executed instructions.

7. The computer system according to claim 1, wherein each of the plurality of processors comprises a microcontroller or microprocessor.

8. The computer system according to claim 1, wherein the reliability metric comprises executing an instruction multiple times on a first processor and performing a redundancy check to compare results between the first execution and the second execution and identifying any errors.

9. The computer system according to claim 1, wherein the performance metric comprises separating a sequence of instructions and executing the separated instructions on two or more processors configured in parallel, and providing results of the executed instructions to another processor.

10. The computer system according to claim 1, wherein each instruction is tagged with a priority or reliability constraint identifier and dispatched by the instruction control unit to a processor.

11. The computer system according to claim 1, wherein a plurality of instructions are tagged with a common priority or reliability constraint identifier and dispatched by the instruction control unit as contiguous sequence.

12. A microprocessor comprising:

at least two execution units capable of performing the same function and adapted to execute instructions based on a performance metric or a reliability metric; and

an instruction control unit to receive instructions and to dynamically assign one of the received instructions for redundant execution by each of the at least two execution units based on the reliability metric, wherein the results of the redundant execution of the received instruction are different from one another, and the instruction control unit assigns another one of the processors to execute the received instruction.

13. The microprocessor of claim 12 wherein the instruction control unit assigns each one of the received instructions to each of the at least two execution units based on the performance metric.

14. The microprocessor of claim 13 further comprising:

at least one additional execution unit for performing a function different from that of the at least two execution units;

wherein the instruction control unit assigns each one of the received instructions to the at least two execution units for execution based upon a defined reliability metric, and assigns another one of the received instructions to the additional execution unit for execution based upon a defined performance metric.