Power transistor arrangement and method for fabricating it

• US 7,250,343 B2
• Filed: 11/12/2004
• Issued: 07/31/2007
• Est. Priority Date: 11/14/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Rieger, Walter, Kotek, Manfred, Haberlen, Oliver, Polzl, Martin
• Primary Examiner(s): Baumeister; B. William
• Assistant Examiner(s): Fulk; Steven J.
• Application Number:
  US10/987,189
• Publication Number:
  US 20050151190A1
• Time in Patent Office: 991 Days
• Field of Search: 438/270, 257/330, 257/341, 257/E21.418
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement (1) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array (3) with cell array trenches (5) each containing a field electrode structure (11) and a gate electrode structure (10). The field electrode structure (11) is electrically conductively connected to the source metallization (15) by a connection trench (6) in the cell array (3).

Claims

1. A method for fabricating a power transistor arrangement, the method comprising:

providing a cell array in a semiconductor substrate, the semiconductor substrate defining a substrate surface;

providing an edge region adjoining the cell array in the semiconductor substrate;

introducing a plurality of cell array trenches and at least one connection trench within the cell array, the at least one connection trench crossing the plurality of cell array trenches;

introducing at least one edge trench in the edge region, the at least one edge trench adjoining the cell array trenches, and the at least one edge trench being wider than each of the plurality of cell array trenches and the at least one connection trench;

applying an insulation layer;

applying a first conductive layer to the insulation layer, the plurality of cell array trenches and the at least one connection trench being substantially completely filled with the first conductive layer, and the at least one edge trench not being completely filled with the first conductive layer;

removing the first conductive layer from the at least one edge trench and causing the first conductive layer to recede in the cell array substantially to the substrate surface;

applying a mask that covers the edge region and the at least one connection trench;

causing the first conductive layer to recede in the cell array trenches in sections not covered by the mask;

providing a gate insulation layer in the cell array trenches in the sections not covered by the mask, the gate insulation layer provided above the first conductive layer that has been caused to recede and forms a field electrode structure; and

implementing a contact connection of the field electrode structure in the region of the connection trench.

2. The method of claim 1 wherein the step of providing the gate insulation layer comprises patterning the gate insulation layer including the steps of

removing sections of the insulation layer that are covered neither by the mask nor by the first conductive layer;

removing the mask; and

providing the gate insulation layer by oxidation of a semiconductor material.

3. The method of claim 2 wherein the step of removing sections of the insulation layer that are covered neither by the mask nor by the first conductive layer comprises a wet-chemical etching process.

4. The method of claim 1 further comprising the steps of:

applying a second conductive layer after the application of the gate insulation layer, the second conductive layer forming a gate electrode structure;

etching back the second conductive layer substantially to the substrate surface such that the cell array trenches are substantially completely filled;

applying an intermediate oxide layer to the cell array and the edge region;

providing source contact trenches in the intermediate oxide layer in the cell array, the source contact trenches operable to provide for the contact connection of source regions and of the connection trench;

providing gate contact holes in the intermediate oxide layer in the edge region, the gate contact holes operable to provide for the contact connection of the gate electrode structure;

providing a gate metallization above the edge region; and

providing a source metallization above the cell array.

5. The method of claim 4 wherein the second conductive layer comprises doped polysilicon.

6. The method of claim 1 wherein the at least one edge trench comprises a plurality of edge trenches and at least one gate connection trench adjoins the edge trenches, the at least one gate connection trenches having substantially the same width as each of the plurality of edge trenches.

7. The method of claim 6 wherein the step of applying the second conductive layer comprises a conformal deposition process and wherein the thickness of the second conductive layer is such that the plurality of edge trenches and the at least one gate connection trench are substantially completely filled.

8. The method of claim 1 wherein the step of applying the insulation layer comprises depositing or growing a field oxide.

9. The method of claim 1 wherein the step of applying the first conductive layer comprises conformal deposition of doped polysilicon.

10. The method of claim 1 wherein the step of causing the first conductive layer to recede in the cell array substantially to the substrate surface comprises an isotropic etching process.

11. The method of claims 1 wherein the step of causing the first conductive layer to recede in the cell array trenches in sections not covered by the mask comprises an isotropic dry etching process.

12. The method of claim 1 further comprising the step of introducing body regions and source regions into the semiconductor substrate, the step of introducing body regions and source regions including implantation of atoms and subsequent heating.

13. The method of claim 12 wherein the body and source regions are implanted before the application of the mask and after partial removal of the first conductive layer.

14. The method of claim 1 wherein the step of applying a mask comprises applying a photosensitive resist layer;

imaging onto the resist layer a structure provided for the mask including use of an exposure mask having the structure and use of a lithography method; and

patterning the resist layer using an etching process.

15. The method of claim 14 wherein the mask substantially covers the edge region and substantially covers the at least one connection trench.

16. The method of claim 15 wherein the mask includes a ridge covering the at least one connection trench and has a width of substantially the width of the at least one connection trench.

17. The method of claim 16 wherein the ridge is widened in the region of a crossover location between the at least one connection trench and one of the plurality of cell array trenches.

18. The method of claim 15 wherein the mask includes a ridge covering the at least one connection trench and has a width in a range from the width of the at least one connection trench to triple the width of the at least one connection trench.

19. The method of claim 15 wherein the mask includes a plurality of pads covering a plurality of crossover locations between the at least one connection trench and at least one source contact trench.

20. The method of claim 1 wherein an anisotropic dry etching process is employed for partial removal of the first conductive layer for formation of the field electrode structure, and the first conductive layer is etched back until the plurality of cell array trenches are filled to a predetermined height.

21. The method of claim 1 wherein an etching process combined from anisotropic and isotropic components is employed for partial removal of the first conductive layer for formation of the field electrode structure.

22. The method of claim 1, wherein the step of removing the first conductive layer includes completely removing the first conductive layer from the at least one edge trench.

23. The method of claim 1, wherein the steps of removing the first conductive layer and causing the first conductive layer to recede, applying a mask, causing the first conductive layer to recede in sections not covered by the mask, providing a gate insulation layer and implementing a contact connection occur in sequential order.