Method for BARC over-etch time adjust with real-time process feedback

• US 7,250,372 B2
• Filed: 07/07/2005
• Issued: 07/31/2007
• Est. Priority Date: 10/22/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Friedmann, James B., Baum, Christopher C.
• Primary Examiner(s): Norton; Nadine
• Assistant Examiner(s): GEORGE, PATRICIA ANN
• Application Number:
  US11/177,145
• Publication Number:
  US 20050245088A1
• Time in Patent Office: 754 Days
• Field of Search: 438/706
• US Class Current: 438/706
• CPC Class Codes: H01L 21/0276 using an anti-reflective coating anti-reflective coating for lithography in general G03F7/09
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: Y10S 430/151 Matting or other surface reflectivity altering material

Abstract

A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CD_resist of the patterned photoresist is measured and a first wafer with median values chosen (101) from a lot. A first time t* is found (102) and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time t_lot is found (104). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot (106).

Claims

1. A method for adjusting bottom anti-reflective coating over-etch time using real time process feedback to achieve a critical dimension CD_final, comprising:

providing a plurality of semiconductor wafers with each of said plurality of wafers, comprising;

a first layer over a semiconductor, a bottom anti-reflective coating layer over said first layer, a patterned photoresist layer over said bottom anti-reflective coating layer wherein said patterned photoresist layer has a first pattern comprising a critical dimension CD_resist;

selecting a first wafer from said plurality of semiconductor wafers;

etching said bottom anti-reflective coating layer of said first wafer to a first critical dimension CD′

_pre;

determining a first over-etch time t* from said CD_resist of said first wafer;

further etching said bottom anti-reflective coating layer of said first wafer from said first critical dimension CD′

_pre to a second critical dimension CD′

_post using said first over-etch time;

using said further etched bottom anti-reflective coating layer, pattern said first layer and measure CD′

_final for said first wafer;

determine a second over-etch time t_lot from said CD′

_final;

etching said bottom anti-reflective coating layer of each of said remaining plurality of wafers to a first critical dimension CD_pre(x), wherein CD_pre(x) is a first critical dimension for a wafer x in said plurality of wafers;

using said second over-etch time t_lot, determine a bottom anti-reflective coating over-etch time t(x) for each of said plurality of wafers, wherein t(x) is a bottom anti-reflective coating over-etch time for a wafer x in said plurality of wafers;

determining a slope S and an intercept I from a CD_bias versus bottom anti-reflective coating over-etch time graph; and

wherein said first over-etch time t* is determined using a relationship t*=(CD′

_resist−

CD_target−

I)/S.

2. The method of claim 1 wherein said second over-etch time t_lot is determined using a relationship t_lot=t*+(CD′

_final−

CD_target)/S.

3. The method of claim 1 wherein the bottom anti-reflective coating over-etch time t(x) is determined using a relationship t(x)=t_lot+(CD_resist(x)−

CD′

_resist)/S.

4. A method for adjusting bottom anti-reflective coating over-etch time using real time process feedback and normalization to achieve a critical dimension CD_final, comprising:

providing a plurality of semiconductor wafers with each of said plurality of wafers, comprising;

a first layer over a semiconductor, a bottom anti-reflective coating layer over said first layer, a patterned photoresist layer over said bottom anti-reflective coating layer wherein said patterned photoresist layer has a first pattern comprising a critical dimension CD_resist;

selecting a first wafer from said plurality of semiconductor wafers;

etching said bottom anti-reflective coating layer of said first wafer to a first critical dimension CD′

_pre;

determining a slope S and an intercept I from a CD_bias versus bottom anti-reflective coating over-etch time graph.

determining a first over-etch time t* from said CD_resist of said first wafer using a relationship t*=(CD′

_resist−

CD_target−

I)/S;

further etching said bottom anti-reflective coating layer of said first wafer from said first critical dimension CD′

_pre to a second critical dimension CD′

_post using said first over-etch time;

using said further etched bottom anti-reflective coating layer, pattern said first layer and measure CD′

_final for said first wafer;

determine a second over-etch time t_lot from said CD′

_final;

etching said bottom anti-reflective coating layer of each of said remaining plurality of wafers to a first critical dimension CD_pre(x), wherein CD_pre(x) is a first critical dimension for a wafer x in said plurality of wafers; and

using said second over-etch time t_lot, determine a bottom anti-reflective coating over-etch time t(x) for each of said plurality of wafers, wherein t(x) is a bottom anti-reflective coating over-etch time for a wafer x in said plurality of wafers.

5. The method of claim 4 wherein said second over-etch time t_lot is determined using a relationship t_lot=t*+(CD′

_final−

CD_target)/S.

6. The method of claim 4 wherein the bottom anti-reflective coating over-etch time t(x) is determined using a relationship t(x)=t_lot+(CD_resist(x)−

CD′

_resist)/S.

7. The method of claim 4 further comprising determining a normalized CD_bias versus wafers etched relationship CD^N_bias(x), wherein CD^N_bias(x) is the normalized value for the x^th wafer etched in a sequence.

8. The method of claim 7 wherein the bottom anti-reflective coating over-etch time t(x) is determined using a relationship t(x)=t_lot+[CD_resist(x)−

CD′

_resist−

CD^N_bias(x)]/S.

9. A method for determining photoresist trim time to achieve a critical dimension CD_final, comprising:

providing a plurality of semiconductor wafers with each of said plurality of wafers, comprising;

a first layer over a semiconductor, an anti-reflective coating layer over said first layer, a patterned photoresist layer over said anti-reflective coating layer wherein said patterned photoresist layer has a first pattern comprising a critical dimension CD_resist;

selecting a first wafer from said plurality of semiconductor wafers;

determining an initial photoresist trim time t_pt*;

trim said patterned photoresist layer using said initial trim time;

using said trimmed photoresist layer, pattern said first layer and measure CD′

_final for said first wafer;

determine a second trim time t_ptlot;

using said second trim time t_ptlot, determine a trim time t_pt(x) for each of said plurality of wafers, wherein t_pt(x) is a patterned photoresist trim time for a wafer x in said plurality of wafers;

determining a slope S and an intercept I from a CD_bias versus over-etch time graph;

determining said initial trim time t_pt* using a relationship t_pt*=(CD′

_resist−

CD_target−

I)/S; and

determining said second photoresist trim time t_ptlot using a relationship t_ptlot=t_pt*+(CD′

_final−

CD_target)/S.