TFT mask ROM and method for making same

• US 7,250,646 B2
• Filed: 10/18/2004
• Issued: 07/31/2007
• Est. Priority Date: 08/13/2001
• Status: Expired due to Fees

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Walker, Andrew J., Petti, Christopher
• Primary Examiner(s): Fourson; George
• Assistant Examiner(s): GARCIA, JOANNIE A
• Application Number:
  US10/965,780
• Publication Number:
  US 20050070060A1
• Time in Patent Office: 1,016 Days
• Field of Search: 257/7, 257/74, 257/278, 257/390, 257/E21.614, 257/E21.662, 257/E21.667, 257/E21.671, 257/E21.677, 257/E27.026, 257/E27.103, 257/E33.077
• US Class Current: 257/278
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/383 Channel doping programmed
• CPC Class Codes: H10B 20/50 having transistors on different levels, e.g. 3D ROM
• CPC Class Codes: H10B 20/60 Peripheral circuit regions
• CPC Class Codes: H10B 20/65 of memory structures of the ROM only type
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.

Claims

1. A mask ROM array, comprising:

a first set of enabled transistors in which each transistor contains a charge storage region; and

a second set of partially or totally disabled transistors;

wherein the first set of transistors and the second set of transistors comprise TFTs.

2. The array of claim 1, wherein each transistor of the second set of transistors contains a charge storage region.

3. The array of claim 1, wherein the second set of TFTs comprises a set of totally disabled TFTs.

4. The array of claim 1, wherein the second set of TFTs comprises a plurality of totally disabled TFTs and a plurality of partially disabled TFTs.

5. The array of claim 1, wherein at least a portion of channel regions of the partially or totally disabled TFTs of the second set have been selectively removed.

6. The array of claim 1, wherein at least a portion of channel regions of the partially or totally disabled TFTs of the second set have been selectively doped to increase a threshold voltage of said TFTs to render said TFTs partially or totally inoperative.

7. The array of claim 1, wherein:

the TFTs are selected from one or more of top gate co-planar TFTs, top gate staggered TFTs, bottom gate co-planar TFTs and bottom gate staggered TFTs; and

the charge storage region comprises a dielectric isolated floating gate, an ONO dielectric film or an insulating layer containing conductive nanocrystals located between a gate and a channel of a TFT.

8. The array of claim 7, further comprising:

a first plurality of spaced apart conductors disposed at a first height above a substrate in a first direction; and

a second plurality of spaced apart rail stacks disposed at a second height in a second direction different from the first direction, each rail stack including;

a first semiconductor layer whose first surface is in contact with said first plurality of spaced apart conductors;

a conductive film; and

the charge storage region disposed between a second surface of the first semiconductor layer and the conductive film.

9. The array of claim 8, wherein:

the first plurality of conductors comprise first rails, each comprising a polysilicon layer in contact with a metal or a metal silicide layer;

the first semiconductor layer comprises a polysilicon layer;

the conductive film comprises a polysilicon layer and a metal silicide layer; and

the TFTs are formed at intersections of adjacent first rails and the second rail stacks, such that the conductive film comprises a gate of the TFTs, portions of the first semiconductor layer comprise TFT channel regions and the polysilicon layers of the first rails comprise at least a portion of TFT source and drain regions.

10. A monolithic three dimensional TFT mask ROM array, comprising a plurality of device levels, wherein at least one device level of the plurality of device levels comprises the array of claim 1.

11. The array of claim 1, wherein the array comprises an array of CMOS TFTs each comprising the charge storage region.

12. The array of claim 11, wherein the programmed array comprises a static random access memory cell and a logic cell.

13. The array of claim 12, wherein the static random access memory array comprises:

the first set of enabled transistors comprising a set of enabled access and inverter TFTs;

the second set of partially or totally disabled transistors comprising a set of disabled isolation TFTs having at least a portion of a channel region removed;

and a third set of isolation TFTs having at least a portion of a channel region removed and at least a portion of the charge storage region removed such that a gate electrode contacts source or drain regions of the TFTs of the third set.

14. The array of claim 12, wherein the logic cell comprises at least one antifuse link connecting a gate electrode and a source or a drain of a TFT.

15. The array of claim 1, further comprising at least one antifuse link connecting a gate electrode and a source or a drain of a TFT.

16. The array of claim 1, wherein at least one transistor of the second set of transistors is programmed by a mask ROM programming technique and at least one other transistor of the first set of transistors is programmed by hot carrier injection or Fowler-Nordheim tunneling.

17. The array of claim 1, wherein the first set of enabled transistors comprises a set of EEPROM transistors.

18. The array of claim 1, wherein each transistor of the first set of enabled transistors contains a charge storage region located between a gate and a channel.

19. A mask ROM array, comprising:

a first set of enabled transistors in which each transistor contains a charge storage region; and

a second set of partially or totally disabled transistors;

wherein at least one transistor of the second set of transistors is programmed by a mask ROM programming technique and at least one other transistor of the first set of transistors is programmed by hot carrier injection or Fowler-Nordheim tunneling.

20. The array of claim 19, wherein the programmed array comprises a static random access memory cell and a logic cell.

21. The array of claim 20, wherein the logic cell comprises at least one antifuse link connecting a gate electrode and a source or a drain of a transistor.

22. The array of claim 19, wherein each transistor of the second set of transistors contains a charge storage region.

23. The array of claim 19, wherein each transistor of the first set of transistors contains the charge storage region located between a gate and a channel.

24. The array of claim 23, wherein each transistor of the second set of transistors contains a charge storage region.

25. The array of claim 23, wherein the charge storage region comprises a dielectric isolated floating gate.

26. The array of claim 23, wherein the charge storage region comprises an ONO dielectric film.

27. The array of claim 23, wherein the charge storage region comprises an insulating layer containing conductive nanocrystals.

28. The array of claim 23, wherein the first set of enabled transistors comprises a set of EEPROM transistors.