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Hybrid planar and FinFET CMOS devices

  • US 7,250,658 B2
  • Filed: 05/04/2005
  • Issued: 07/31/2007
  • Est. Priority Date: 06/26/2003
  • Status: Active Grant
First Claim
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1. An integrated semiconductor circuit comprising:

  • at least one FinFET and at least one planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, said at least one planar single gated FET comprising an active device region that includes a patterned top semiconductor layer of the silicon-on-insulator substrate and said at least one FinFET has a vertical channel that is perpendicular to the at least one planar single gated FET, wherein said vertical channel has a height that is greater than said patterned top semiconductor layer of said at least one planar single gated FET.

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