Hybrid planar and FinFET CMOS devices

• US 7,250,658 B2
• Filed: 05/04/2005
• Issued: 07/31/2007
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Min, Kanarsky, Thomas S., Doris, Bruce B., Boyd, Diane C., Kedzierski, Jakub T., Leong, Meikei
• Primary Examiner(s): Wilczewski; M.
• Assistant Examiner(s): Perkins; Pamela E
• Application Number:
  US11/122,193
• Publication Number:
  US 20050263831A1
• Time in Patent Office: 818 Days
• Field of Search: 257/328, 257/350, 257/401
• US Class Current: 257/350
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

Claims

1. An integrated semiconductor circuit comprising:

at least one FinFET and at least one planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, said at least one planar single gated FET comprising an active device region that includes a patterned top semiconductor layer of the silicon-on-insulator substrate and said at least one FinFET has a vertical channel that is perpendicular to the at least one planar single gated FET, wherein said vertical channel has a height that is greater than said patterned top semiconductor layer of said at least one planar single gated FET.

2. The integrated semiconductor circuit of claim 1 wherein the top semiconductor layer is comprised of Si.

3. The integrated semiconductor circuit of claim 1 wherein the buried insulating layer is comprised of an oxide.

4. The integrated semiconductor circuit of claim 1 wherein the vertical channel has a (110) surface orientation, and the at least one planar single gated FET has a (100) surface orientation.

5. The integrated semiconductor circuit of claim 1 wherein the at least one FinFET is a double gate device.

6. The integrated semiconductor circuit of claim 1 wherein the vertical channel has a (100) surface orientation, and the at least one planar single gated FET has a (110) surface orientation.