Display control device

• US 7,250,943 B2
• Filed: 06/14/2004
• Issued: 07/31/2007
• Est. Priority Date: 06/13/2003
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Kamiyama, Masayuki
• Primary Examiner(s): Hjerpe; Richard
• Assistant Examiner(s): Said; Mansour M.
• Application Number:
  US10/867,567
• Publication Number:
  US 20050012727A1
• Time in Patent Office: 1,142 Days
• Field of Search: 345/87, 345/95, 345/157, 345/169, 345204-205, 345210-211, 345/102, 345/214, 455/95, 455/574, 455/343.1, 455/127.1, 379/433.01, 379/433.06, 379/433.07, 379/433.1
• US Class Current: 345/204
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory

Abstract

A display control device is provided to realize a bypass function of a display controller by using fewer chip select signal lines without causing a malfunction. In the display control device, bypassing a display controller is realized by using one chip select signal line and one signal line for the general ports provided to a host. Therefore, bypassing the display controller can be realized by using fewer chip select signal lines. In addition, malfunctioning is prevented when a bypass mode is provided because the switching to/from the bypass mode and the transmission of the CS signal are not performed by one common chip select signal line.

Claims

1. A display control device, comprising:

a host performing an instruction to display an image on a display; and

a display controller coupled to the host by a predetermined number of chip select signal lines and general signal lines, the display controller performing predetermined image processing based on an instruction from the host and outputting a control signal to a display driver directly controlling the display, wherein

the display controller includes;

a halt state in which operation is halted in a predetermined case; and

a bypass function with which the host accesses the display driver when the display controller is in the halt state; and

the host is switchable between a normal state in which a chip select signal is outputted to the display controller and a bypass state in which the chip select signal is outputted to the display driver, the switching being accomplished by using one of the chip select signal lines and one of the general signal lines.

2. The display control device according to claim 1, wherein the host outputs the chip select signal to the display controller via the one chip select signal line, and outputs a signal to switch whether the bypass function is used via the one general signal line.

3. The display control device according to claim 1, wherein:

the one chip select signal line is coupled as an internal chip select signal line for the display controller;

the one general signal line is coupled as a chip select signal line for the display driver when bypassing, in the display controller; and

the host switches whether the bypass function is used by making the chip select signal and the general signal equal to predetermined output values.

4. The display control device according to claim 1, wherein:

the one chip select signal line is coupled to a first selector which switches whether an input signal is outputted to an internal chip select signal line for the display controller, and to a second selector which switches whether an input signal is outputted to a chip select signal line for the display driver when bypassing, in the display controller; and

the one general signal line is coupled as a selecting instruction signal for the first and second selectors,

the chip select signal is alternatively outputted to the internal chip select signal line and the one chip select signal line for the display driver by one of the first and second selectors corresponding to the output value of the general signal.