Circuit structure and signal encoding method for a serial ATA external physical layer

• US 7,251,280 B2
• Filed: 07/25/2003
• Issued: 07/31/2007
• Est. Priority Date: 03/13/2003
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chiang, Chinyi
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US10/626,587
• Publication Number:
  US 20040153683A1
• Time in Patent Office: 1,467 Days
• Field of Search: 375/219, 375/222, 375/241, 375/242, 375/257, 341/143, 710/33, 710/38, 710/51, 710/52, 714/748, 714/749
• US Class Current: 375/242
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0676 Magnetic disk device

Abstract

A circuit structure and signal encoding method for a serial ATA external physical layer is provided. The circuit structure and signal encoding method thereof is capable of reducing the number of interface signals of a serial ATA external physical layer, essentially comprising a decoder/encoder, a serializer/deserializer, a phase locked loop, at least one transmitter, at least one receiver, and at least one OOB signal detector, encoding various control signals and various status signals, required for the connection between the decoder/encoder and a storage medium controller, into data signals using signals other than a data conversion requirement of 8 bits and 10 bits, by the decoder/encoder, in order for greatly reducing the number of interface signals required for the connection between the external physical layer and a main control chip.

Claims

1. A circuit structure for a serial Advanced Technology Attachment (ATA) external physical layer comprising:

a decoder/encoder connected to a storage medium controller via a set of parallel signal transmission lines and a set of parallel signal receiving lines for decoding a parallel transmission signal originated from said storage medium controller into a parallel transmission data signal and at least one control signal;

at least one serializer/deserializer connected to said decoder/encoder for the conversion of said parallel transmission data signal into a serial transmission data signal;

at least one phase locked loop connected to said decoder/encoder and said at least one serializer/deserializer, respectively, for receiving said at least one control signal originated from said decoder/encoder, as well as generating clock signals required for the operation of said physical layer and transmitting a reference clock signal to said storage medium controller;

a plurality of transmitters, connected to said serializer/deserializer, each of said transmitters being used to transmit said serial transmission data signal to a serial ATA device connected thereto via a set of serial signal transmission lines;

a plurality of receivers connected to said serializer/deserializer, each of said receivers being used to transmit a serial receiving data signal received from said serial ATA device connected thereto to said serializer/deserializer, and then said serial receiving data signal being converted into a parallel receiving data signal by said serializer/deserializer for transmitting to said decoder/encoder; and

at least one out of band (OOB) signal detector connected to receiving signal lines of said corresponding receivers, respectively, for detecting the operation condition of said serial ATA device and transmitting at least one set of detected status signals to said decoder/encoder, said parallel receiving data signal and said status signals then being encoded into a parallel receiving signal by said decoder/encoder and, afterward, transmitted to said storage medium controller via said set of parallel signal receiving lines.

2. The circuit structure according to claim 1, wherein said decoder/encoder comprises a decoder and an encoder, said decoder being connected to said storage medium controller via said set of parallel signal transmission lines, and said encoder being connected to said storage medium controller via said set of parallel signal receiving lines.

3. The circuit structure according to claim 1, wherein said serializer/deserializer comprises at least one serializer and at least one deserializer.

4. The circuit structure according to claim 3, wherein an elastic buffer is provided between said at least one deserializer and said decoder/encoder.

5. The circuit structure according to claim 3, further comprising at least one selector, one input of which being connected to said at least one serializer, the other input thereof being connected to at least one receiver, and an output thereof being connected to said at least one deserializer.

6. The circuit structure according to claim 1, wherein said at least one phase locked loop comprises at least one transmission phase locked loop and at least one receiving phase locked loop.

7. The circuit structure according to claim 1, wherein said at least one control signal comprises reset signals, power control signals, transmission valid signals, and one of the combinations thereof.

8. The circuit structure according to claim 7, wherein said at least one control signal further comprises control signals and receiving rate control signals.

9. The circuit structure according to claim 1, wherein said status signals comprise communication initialization signals, communication wake up signals;

receiving squelch signals, receiving phase lock loop ready signals, and one of the combinations thereof.

10. The circuit structure according to claim 1, wherein said at least one phase locked loop has a function of transmission rate switching.

11. The circuit structure according to claim 1, further comprising a power controller for controlling the reset and other power states of said physical layer and connected said serial ATA device.

12. The circuit structure according to claim 1, wherein said circuit structure is capable of being integrated into a chip.

13. The circuit structure according to claim 1, wherein only one integrated drive electronics (IDE) bus is needed for connection between said physical layer and said storage medium controller.