Phase detector

• US 7,251,573 B2
• Filed: 08/11/2004
• Issued: 07/31/2007
• Est. Priority Date: 08/29/2003
• Status: Expired due to Fees

• Current Assignee: Funai Electric Co., Ltd. (Funai Electric Holdings Company Limited)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Sanduleanu, Mihai Adrian Tiberiu, Stikvoort, Eduard Ferdinand
• Primary Examiner(s): Wachsman, Hal
• Assistant Examiner(s): Desta, Elias
• Application Number:
  US10/569,125
• Publication Number:
  US 20070021933A1
• Time in Patent Office: 1,084 Days
• Field of Search: 702/72, 702/79, 702/182, 702/189, 331/2, 331/25, 329/304, 329/311, 375/226, 375/260, 375/373, 375/375
• US Class Current: 702/79
• CPC Class Codes: H03D 13/003 in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

The present invention concerns a phase Detector for detecting a phase difference between a data clock DATA-CLK and a reference clock REF-CLK using a data signal DATA. A trasnsition of the data signal DATA is synchronous with a transition of the data clock DATA-CLK. The data clock DATA-CLK and the reference clock REF-CLK have the same frequency. The phase detector includes first signal generator for generating a first binary signal ERRQ a second signal generator for generating a second binary signal ERRI. The pulse width of the second binary signal ERRI is equal to a second time difference ΔT2 between a transition of the data signal DATA and a transition of the second reference clock signal CKI adjacent to the transition of the data signal DATA.

Claims

1. Phase Detector for detecting a phase difference between a data clock (DATA-CLK) and a reference clock (REF-CLK) using a data signal (DATA), wherein a transition of the data signal (DATA) is synchronous with a transition of the data clock (DATA-CLK) and the data clock (DATA-CLK) and the reference clock (REF-CLK) have the same frequency, comprising:

a first signal generator (42) for generating a first binary signal (ERRQ), a pulse width of which is equal to a first time difference (Δ

T1) between a transition of the data signal (DATA) and a transition of a first reference clock signal (CKQ) adjacent to the transition of the data signal (DATA), wherein the first signal generator comprises an input for receiving the first reference clock signal (CKQ) and an input for receiving the data signal (DATA), wherein the first reference clock (CKQ) has half the frequency of the reference clock (REF-CLK) and is synchronous with the reference clock,

a second signal generator (40) for generating a second binary signal (ERRI), a pulse width of which is equal to a second time difference (Δ

T2) between a transition of the data signal (DATA) and a transition of the second reference clock signal (CKI) adjacent to the transition of the data signal (DATA), wherein the second signal generator (40) comprises an input for receiving the second reference clock (CKI) and an input for receiving the data signal (DATA),

output signal generator (44) for generating an output signal representative of the phase difference between the data clock (DATA-CLK) and the reference clock (REF-CLK), wherein the output signal is equal to ERRQ−

2*(ERRQ AND ERRI) and AND represents a logical AND-operation, or the output is equal to (ERRQ XOR ERRI)−

ERRI, wherein XOR represents a logical XOR-operation.

2. Phase detector for detecting a phase difference according to claim 1, wherein the first signal generator comprises two D-latches that are both adapted to receive the data signal (DATA), a first one of the two D-latches of the first signal generator is adapted to receive the first reference clock signal and a second one of the two D-latches of the first signal generator is adapted to receive an inverted first reference clock.

3. Phase detector for detecting a phase difference according to claim 2, wherein the second signal generator comprises two D-latches that are both adapted to receive the data signal (DATA), a first one on the two D-latches of the second signal generator is adapted to receive the second reference clock and a second one of the two D-latches of the second signal generator is adapted to receive an inverted second reference clock.

4. Phase detector according to claim 3, wherein signals output by the two D-latches of the first or second signal generator are either output to a XOR-gate or an XNOR-gate.

5. Phase detector for detecting a phase difference according to claim 1, wherein the output signal generator (44) comprises an AND-gate having two inputs and an output, the inputs of the AND-gate receive the first (ERRQ) and the second binary signal (ERRI), the output signal generator (44) comprises a multiplicator (*2) for multiplying the output of the AND-gate by 2, the output signal generator (44) comprises a subtractor (SUM) for subtracting the output of the multiplicator (*2) from the first binary signal (ERRQ), said subtractor having an output (PD) representing the output of the phase detector.

6. Phase detector according to claim 1, wherein the output signal generator comprises a first OR-gate (OR), wherein both inputs of the first OR-gate (OR) are connected to the first binary signal (ERRQ), the output signal generator comprises a second OR-gate, wherein a first input of the second OR-gate is connected to the first binary signal (ERRQ) an a second input of the second OR-gate is connected to the second binary signal (ERRI), and the output signal generator comprises a charge pump connected to an output of the first and second OR-gate (OR), the charge pump is adapted to multiply the output of the second OR-gate by 2 and subtract the result from the output of the first OR-gate.

7. Phase detector according to claim 1, wherein the output signal generator comprises a first XOR-gate, said first XOR-gate having an input receiving the first binary signal (ERRQ) and an input receiving the second binary signal (ERRI), the output signal generator comprises a second XOR-gate, said second XOR-gate having an input receiving the second binary signal (ERRI) and an input receiving a logical 0, the output signal generator (ERRQ) comprises charge pump, said charge pump being adapted to subtract an output of the second XOR-gate from the output of the first XOR-gate.

8. Method for detecting a phase difference between a data clock (DATA-CLK) and a reference clock (REF-CLK) using a data signal (DATA), wherein a transition of the data signal (DATA) is synchronous with a transition of the data clock (DATA-CLK), comprising the steps of:

receiving a first reference clock signal (CKQ) and a second reference clock (CKI) signal both having the same frequency (f) half as large as the frequency of the reference clock (REF-CLK), and a phase difference between the first reference clock signal (CKQ) and the second reference clock signal (CKI) is equal to 1/(4f),

generating a first binary signal (ERRQ), a pulse width of which is equal to a first time difference (Δ

T1) between a transition of the data signal (DATA) and a transition of a first reference clock signal (CKQ) adjacent to the transition of the data signal (DATA),

generating a second binary signal (ERRI), a pulse width of which is equal to a second time difference (Δ

T2) between a transition of the data signal (DATA) and a transition of the second reference clock signal (CKI) adjacent to the transition of the data signal (DATA),

generating an output signal representative of the phase difference between the data clock (DATA-CLK) and the reference clock (REF-CLK), wherein the output signal is equal to ERRQ−

2*(ERRQ AND ERRI) and AND represents a logical AND-operation.