Store and forward switch device, system and method

• US 7,251,704 B2
• Filed: 08/23/2002
• Issued: 07/31/2007
• Est. Priority Date: 08/23/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Harriman, David, Solomon, Gary A.
• Primary Examiner(s): Auve; Glenn A.
• Assistant Examiner(s): Cleary; Thomas J.
• Application Number:
  US10/226,838
• Publication Number:
  US 20040039986A1
• Time in Patent Office: 1,803 Days
• Field of Search: 710/38, 710/52, 710316-317, 710/30, 710/305, 714/52, 714/758, 714/799, 714800-801, 714/807, 370/218, 370/242, 370/244, 370/389, 370/392, 370/912
• US Class Current: 710/316
• CPC Class Codes: H04L 49/252 Store and forward routing
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/555 Error detection

Abstract

Disclosed are a system and method for forwarding data packets from ingress ports to egress ports on a switch. A forwarding circuit may commence forwarding data packets from an ingress port through a switch fabric to a transmit queue of an egress port prior to completion of a checksum operation.

Claims

1. A method comprising:

receiving a data packet at an ingress port of a switch coupling a plurality of components within a processing platform in a single computer including a processor, a root device, and one or more peripheral devices, the data packet being received at the ingress port from a first component, the first component being one of the processor, the root device, and the one or more peripheral devices;

the switch initiating a checksum operation on a portion of the received data packet to validate the data packet, while the data packet is being received and before the data packet is received completely;

substantially concurrently with respect to receiving the data packet and the checksum operation, commencing forwarding the received portion of the data packet through a switch fabric of the switch to a transmit queue of an egress port of the switch prior to completion of the checksum operation performed at the ingress port, the egress port coupled to a second component of the processing platform, the second component being one of the processor, the root device, and the one or more peripheral devices and different than the first component, wherein the second component receives a packet invalid symbol inserted at the tail end of the data packet to initiate a first link level retry from the switch for retransmission of the data packet, and wherein the switch initiates a second link level retry on the ingress port for retransmission of the data packet in response to the first link level retry;

the switch sending a configuration header to the processor; and

in response to the configuration header, the processor allocating communication resources at the processing platform to communicate with a virtual bridge corresponding to a port of the switch.

2. The method of claim 1, further comprising:

transmitting a CRC indication based on the checksum operation from the ingress port to the transmit queue of the egress port after the data packet has been completely forwarded to the transmit queue of the egress port; and

selectively transmitting the forwarded data packet from the transmit queue of the egress port to a the second component if the CRC indication is an a valid CRC indication resulted from the checksum operation performed at the ingress port.

3. The method of claim 2, further comprising selectively dropping the forwarded data packet from the transmit queue of the egress port in response to an invalid CRC indication from the checksum operation.

4. The method of claim 3, further comprising the ingress port inserting the packet invalid symbol into a tail portion of the data packet in response to an invalid CRC indication from the checksum operation, wherein the egress port performs dropping the data packet from the transmit queue in response to the packet invalid symbol received from the ingress port.

5. The method of claim 4, further comprising:

the egress port starting transmitting the data packet to the second component before the data packet has been received completely at the transmit queue of the egress port from the ingress port; and

in response to the invalid CRC indication received at an end of the data packet, the egress port transmitting the invalid CRC indication to the second component, wherein the second component drops the data packet received from the egress port in response to the invalid CRC indication.

6. The method of claim 5, further comprising:

extracting destination information from a portion of the received data packet based upon a data packet type associated with the received data packet; and

selecting the egress port based upon the destination information, wherein the egress port is communicatively coupled to the second component identified by the destination information.

7. The method of claim 6, further comprising:

selecting the egress port based upon a physical address of the second component specified in the received data packet if the received data packet is associated with a request data packet type; and

selecting the egress port based upon an identifier of a source of a request data packet if the received data packet is associated with a request completion data packet type.

8. The method of claim 7, wherein the virtual bridge is a virtual PCI-to-PCI bridge.

9. The method of claim 8, wherein the configuration header identifies an additional virtual PCI-to-PCI bridge coupled to a secondary bus of the virtual PCI-to-PCI bridge, the additional virtual PCI-to-PCI bridge corresponding to an additional port of the switch.

10. The method of claim 9, wherein a virtual device is coupled with the additional virtual PCI-to-PCI bridge.

11. The method of claim 10, wherein the virtual device is coupled with the additional port of the switch through a serial link, and wherein a PCI bus segment number is associated with the serial link in the communication resources.

12. The method of claim 8, wherein the communication resources have an address range for forwarding messages from a primary bus to a secondary bus of the virtual PCI-to-PCI bridge.

13. The method of claim 1, further comprising:

determining an availability of the egress port to transmit the received data packet; and

selectively forwarding the received data packet to the transmit queue based upon the availability of the egress port.

14. A switch comprising:

a plurality of ports coupled to a switch fabric, at least one port comprising a transmit queue, the plurality of ports capable of being communicatively coupled to a plurality of components within a processing platform in a single computer including a processor, a root device, and one or more peripheral devices;

a checksum circuit to execute a checksum operation on at least a portion of a data packet received at an ingress port while the data packet is being received and before the data packet is received completely, the ingress port communicatively coupled to a first component of the processing platform and the first component being one of the processor, the root device, and the one or more peripheral devices;

a forwarding circuit to commence, substantially concurrently with respect to the checksum operation, forwarding the received portion of the data packet through the switch fabric to a transmit queue of an egress port prior to completion of the checksum operation performed at the ingress port, the egress port communicatively coupled to a second component of the processing platform and the second component being one of the processor, the chip set, and the one or more peripheral devices different than the first component, wherein the second component receives a packet invalid symbol inserted at the tail end of the data racket to initiate a first link level retry from the switch for retransmission of the data packet, and wherein the switch initiates a second link level retry on the ingress port for retransmission of the data packet in response to the first link level retry; and

a responding circuit sending a configuration header to the processor, the processor allocating resources at the processing platform to communicate with a virtual bridge corresponding to a port of the switch in response to the configuration header.

15. The switch of claim 14, wherein the egress port comprises logic to selectively transmit the forwarded data packet from the transmit queue in response to a valid CRC indication from the checksum operation.

16. The switch of claim 15, wherein the egress port comprises logic to selectively drop the forwarded data packet from the transmit queue in response to an invalid CRC indication from the checksum operation.

17. The switch of claim 14, further comprising logic to insert the packet invalid symbol into the forwarded data packet in response to an invalid CRC indication from the checksum operation.

18. The switch of claim 14, wherein the forwarding circuit comprises logic to select the egress port based upon a portion of the received data packet.

19. The switch of claim 18, wherein the forwarding circuit further comprises:

logic to associate the received data packet with a data packet type based upon a portion of the received data packet;

logic to extract destination information from a portion of the received data packet based upon the associated data packet type; and

logic to select the egress port based upon the destination information.

20. The switch of claim 19, wherein the forwarding circuit further comprises:

logic to select the egress port based upon a physical address of a destination specified in the received data packet if the received data packet is associated with a request data packet type; and

logic to select the egress port based upon an identifier of a source of a request data packet if the received data packet is associated with a request completion data packet type.

21. A processing platform system comprising:

a switch coupled to a processor in a single computer comprising;

a plurality of ports coupled to a switch fabric, at least one port comprising a transmit queue;

a checksum circuit to execute a checksum operation on at least a portion of a data packet received at an ingress port while the data packet is being received and before the data packer is received completely;

a forwarding circuit to, substantially concurrently with respect to the checksum operation, commence forwarding the received data packet through the switch fabric to a transmit queue of an egress port prior to completion of the checksum operation performed to the ingress port, the egress port being coupled to a component, wherein the component receives a packer invalid symbol inserted at the tail end of the data packet to initiate a first link level retry from the switch for retransmission of the data packet, and wherein the switch initiates a second link level retry on the ingress port for retransmission of the data packet in response to the first link level retry; and

a responding circuit to send a configuration header to the processor, the processor allocating resources at the processing platform to communicate with a virtual bridge corresponding to a port of the switch in response to the configuration header;

a host processing system coupled to an upstream port of the switch through a root device; and

one or more devices coupled to downstream ports of the switch, wherein the ingress and egress ports are respectively one of the upstream and downstream ports of the switch, and wherein the switch couples the host processing system and the one or more devices via one or more interconnect within the processing platform system.

22. The system of claim 21, wherein the egress port comprises logic to selectively transmit the forwarded data packet from the transmit queue in response to a valid CRC indication from the checksum operation.

23. The system of claim 22, wherein the egress port comprises logic to selectively drop the forwarded data packet from the transmit queue in response to an invalid CRC indication from the checksum operation.

24. The system of claim 21, wherein the forwarding circuit further comprises:

logic to associate the received data packet with a data packet type based upon a portion of the received data packet;

logic to extract destination information from a portion of the received data packet based upon the associated data packet type; and

logic to select the egress port based upon the destination information.

25. The system of claim 24, wherein the forwarding circuit further comprises:

logic to select the egress port based upon a physical address of a destination specified in the received data packet if the received data packet is associated with a request data packet type; and

logic to select the egress port based upon an identifier of a source of a request data packet if the received data packet is associated with a request completion data packet type.

26. The system of claim 21, wherein the forwarding circuit further comprises:

logic to determine an availability of the egress port to transmit the received data packet; and

logic to selectively forward the received data packet to the transmit queue based upon the availability of the egress port.

27. The system of claim 21, wherein at least one downstream port is coupled to a device selected from a group consisting of a graphics controller, a small computer system interface, an Ethernet controller, a Fibrechannel interface and a serial ATA device.