Apparatus and methods having a command sequence
First Claim
Patent Images
1. A method to control writing to a memory device comprising:
- controlling a device to generate a command sequence of n cycles to control writing data to the memory device, each cycle including data, an address, and a specific command, the specific command generated by applying a set combination of control signals;
providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n;
providing arbitrary data in a cycle in which a write command is generated and arranged in one of a first cycle through the mth cycle, the arbitrary data being data not for operational use by the memory; and
transmitting the command sequence from the device to turn on a data input buffer in the memory device and to write to the memory device.
8 Assignments
0 Petitions
Accused Products
Abstract
Power consumption by a memory device is optimized by maintaining data input buffers in an off state until a command sequence containing a write command is received by the memory. A command sequence is provided to the memory device where the command sequence was constructed by generating a command sequence of n cycles and providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, where m is less than n. The data input buffers are returned to an off state upon completion of a program or erase operation defined in the received command sequence.
78 Citations
80 Claims
-
1. A method to control writing to a memory device comprising:
-
controlling a device to generate a command sequence of n cycles to control writing data to the memory device, each cycle including data, an address, and a specific command, the specific command generated by applying a set combination of control signals; providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n; providing arbitrary data in a cycle in which a write command is generated and arranged in one of a first cycle through the mth cycle, the arbitrary data being data not for operational use by the memory; and transmitting the command sequence from the device to turn on a data input buffer in the memory device and to write to the memory device. - View Dependent Claims (2, 3)
-
-
4. A method to control writing to a memory device comprising:
-
controlling a device to generate a command sequence of n cycles to control writing data to the memory device; providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence occurs for m equal to one; and transmitting the command sequence from the device to turn on a data input buffer in the memory device and to write to the memory device.
-
-
5. A method to control writing to a memory device comprising:
-
controlling a device to generate a command sequence of n cycles to control writing data to the memory device; providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence is performed with the mth cycle being a second cycle containing a write command; and transmitting the command sequence from the device to turn on a data input buffer in the memory device and to write to the memory device.
-
-
6. A method to control writing to a memory device comprising:
-
controlling a device to generate a command sequence of n cycles to control writing data to the memory device; providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein the method further includes providing arbitrary data in a cycle in which a write command is generated and arranged in one of a first cycle through the mth cycle, the arbitrary data being data not for operational use by the memory; and transmitting the command sequence from the device to turn on a data input buffer in the memory device and to write to the memory device.
-
-
7. A method to control writing to a memory device comprising:
-
controlling a device to generate a command sequence of n to control writing data to the memory device; generating valid data provided for a first plurality of data input buffers in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n; providing arbitrary data in a cycle in which a write command is generated and arranged in one of a first cycle through the mth cycle, the arbitrary data being data not for operational use by the memory; and transmitting the command sequence from the device to write to the memory device.
-
-
8. A method to control writing to a memory device comprising:
-
controlling a device to generate a command sequence of n cycles to control writing data to the memory device; generating valid data provided for a first plurality of data input buffers in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein the method further includes generating valid data provided for a second plurality of data input buffers on a first cycle containing a write command of the command sequence; and transmitting the command sequence from the device to write to the memory device.
-
-
9. A method to control writing to a memory device comprising:
-
controlling a device to generate a command sequence of n cycles to control writing data to the memory device; generating valid data provided for a first plurality of data input buffers in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein the method further includes generating valid data provided for a second plurality of data input buffers on a kth cycle of the command sequence, k being less than m, the kth cycle containing a write command; and transmitting the command sequence from the device to write to the memory device.
-
-
10. A method to control writing to a memory device comprising:
-
controlling a device to generate a command sequence of n cycles to send data to the memory device; generating valid data provided for T data input buffers, the T data input buffers grouped into R sets of data input buffers, wherein valid data is provided for a jth set of the R sets of data input buffers on a mjth cycle of the command sequence, 1≦
j≦
R and 1≦
mj≦
n, the mjth cycle containing a write command; andtransmitting the command sequence from the device to write to the memory device. - View Dependent Claims (11)
-
-
12. A method to control writing to a memory device comprising:
-
receiving a write request in a device; controlling the device to generate a command sequence of n cycles in response to the write request including determining a value for n, the command sequence to control writing data to the memory device; and providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n; providing arbitrary data on a first cycle through the mth cycle; and transmitting the command sequence from the device to write to the memory device. - View Dependent Claims (13)
-
-
14. A method to control writing to a memory device comprising:
-
receiving a write request in a device to control writing data to the memory device; and controlling the device to generate a command sequence of n cycles in response to the write request; providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence occurs for m equal to one; and transmitting the command sequence from the device to turn on a data input buffer in the memory device and to write to the memory device.
-
-
15. A method to control writing to a memory device comprising:
-
receiving a write request in a device to control writing data to the memory device; and controlling the device to generate a command sequence of n cycles in response to the write request, after receiving the write request; and providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein the method further includes providing arbitrary data on a first cycle through the mth cycle;
the arbitrary data being data not for operating use by the memory; andtransmitting the command sequence from the device to turn on a data input buffer in the memory device and to write to the memory device.
-
-
16. A method to control writing to a memory device comprising:
-
receiving a write request in a device to send data to the memory device; controlling the device to generate a command sequence of n cycles in response to the write request including determining a value for n, to control writing the data to the memory device; providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein the valid data is provided for a first plurality of data input buffers; providing arbitrary data on a first cycle through the mth cycle; and transmitting the command sequence from the device to write to the memory device.
-
-
17. A method to control writing to a memory device comprising:
-
receiving a write request in a device to send data to the memory device; controlling a device to generate a command sequence of n cycles in response to the write request, after receiving the write request, to control writing data to the memory device; providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein the valid data is provided for a first plurality of data input buffers, wherein the method further includes providing arbitrary data on a first cycle through the mth cycle; and transmitting the command sequence from the device to write to the memory device.
-
-
18. A method to control writing to a memory device comprising:
-
receiving a write request in a device to send data to the memory device; controlling the device to generate a command sequence of n cycles in response to the write request to control writing the data to the memory device; providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein the valid data is provided for a first plurality of data input buffers, wherein the method further includes providing valid data for a second plurality of data input buffers on a first cycle of the command sequence; and transmitting the command sequence from the device to write to the memory device.
-
-
19. A method to control writing to a memory device comprising:
-
receiving a write request in a device to send data to the memory device; controlling the device to generate a command sequence of n cycles in response to the write request to control writing the data to the memory device; providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein the valid data is provided for a first plurality of data input buffers, wherein the method further includes providing valid data for a second plurality of data input buffers on a first cycle of the command sequence containing a write commend; and transmitting the command sequence from the device to write to the memory device.
-
-
20. A method to control writing to a memory device comprising:
-
receiving a write request in a device to send data to the memory device; controlling the device to generate a command sequence of n cycles in response to the write request to control writing the data to the memory device; providing valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein the valid data is provided for a first plurality of data input buffers, wherein the method further includes generating valid data provided for a second plurality of data input buffers on a kth cycle of the command sequence, k being less than m, the kth cycle containing a write command; and transmitting the command sequence from the device to write to the memory device. - View Dependent Claims (21)
-
-
22. A method of operating a memory device comprising:
-
receiving a command sequence of n cycles; detecting a write command and a valid address in the mth cycle of the command sequence, m<
n; andplacing data input buffers of the memory device into an on state in response to detecting a write command and a valid address in the mth cycle of the command sequence. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31)
-
-
32. A method of operating a memory device comprising:
-
receiving a command sequence of n cycles; detecting a write command and a valid address in the mth cycle of the command sequence, m<
n; andplacing a first plurality of data input buffers of the memory device into an on state in response to detecting a write command and a valid address in the mth cycle of the command sequence. - View Dependent Claims (33, 34, 35, 36)
-
-
37. A method of operating a memory device comprising:
-
receiving a command sequence of n cycles; detecting a first cycle of a command sequence; and placing T data input buffers of the memory device in an on state, the T data input buffers grouped into R sets of data input buffers, a jth set of the R sets of data input buffers is placed in an on state beginning for a mjth cycle of the command sequence for all jth sets, 1≦
j≦
R and 1≦
mj≦
n.
-
-
38. A memory device comprising:
-
control circuitry; and data input buffers configured in an off state, the data input buffers switchable to an on state responsive to the control circuitry detecting an externally generated command sequence of n cycles, wherein the control circuitry is configured to place the data input buffers into an off state upon completing an execution of an operation defined by the command sequence. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47)
-
-
48. A memory device comprising:
-
control circuitry; and a first plurality of data input buffers configured in an off state, wherein the first plurality of data input buffers are placed in an on state in response to the control circuitry detecting a first m cycles of an externally generated command sequence of n cycles, m<
n, wherein the control circuitry is configured to place the data input buffers into an off state upon completing an execution of an operation defined by the command sequence. - View Dependent Claims (49, 50, 51)
-
-
52. A memory device comprising:
-
control circuitry; and T data input buffers configured in an off state, the T data input buffers grouped into R sets of data input buffers, wherein a jth set of the R sets of data input buffers is placed in an on state beginning for a mjth cycle of an externally generated command sequence of n cycles in response to the control circuitry detecting a reception of a command sequence for all jth sets, 1≦
j≦
R and 1≦
mj≦
n. - View Dependent Claims (53, 54, 55, 56)
-
-
57. A memory module comprising:
-
input ports for receiving a write request; a load command unit coupled to the input ports for converting the received write request into a command sequence of n cycles having valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n, wherein the load command unit is configured to determine a value of n and to generate arbitrary data in each cycle where a write command is generated before generating the mth cycle in the n cycle command sequence; and output ports coupled to the load command unit for directing the command sequence to a memory device. - View Dependent Claims (58, 59, 60)
-
-
61. A memory module comprising:
-
input ports for receiving a write request; a load command unit coupled to the input ports for converting the received write request into a command sequence of n cycles having valid data in each cycle in which a write command is generated after a mth cycle of the command sequence, m being less than n; and output ports coupled to the load command unit for directing the command sequence to a memory device to turn on a data input buffer in the memory device and to write to the memory device, wherein the load command unit is configured to generate a write command with associated valid data during a mth cycle in the n cycle command sequence after generating a cycle with a first write command, wherein m is less than n, wherein the load command unit is configured to generate arbitrary data in each cycle where a write command is generated before generating the mth cycle in the n cycle command sequence.
-
-
62. An information handling system comprising:
-
a processor; a load command unit coupled to the processor for receiving a write request form the processor; and a memory device coupled to the load command unit, wherein the load command unit is configured to generate a command sequence of n cycles to the memory device with valid data provided in each cycle containing a write command after a m cycle, mth being less than n, and the load command unit is configured to generate arbitrary data in each cycle where a write command is generated before generating the mth cycle in the n cycle command sequence, the command sequence to turn on a data input buffer in the memory device and to write to the memory device. - View Dependent Claims (63)
-
-
64. An information handling system comprising:
-
a processor; a load command unit coupled to the processor for receiving a write request form the processor; and a memory device coupled to the load command unit, wherein the load command unit is configured to generate a command sequence of n cycles to the memory device with valid data provided in each cycle containing a write command after a mth cycle, m being less than n, wherein the memory device comprises data input buffers configured in an off state until the memory device determines the reception of a command sequence. - View Dependent Claims (65, 66)
-
-
67. An information handling system comprising:
-
a processor; and a memory device coupled to the processor, the memory device comprising; control circuitry; and data input buffers configured in an off state, the data input buffers switchable to an on state responsive to the control circuitry detecting an externally generated command sequence of n cycles, wherein the control circuitry is configured to place the data input buffers into an off state upon completing an execution of an operation defined by the command sequence. - View Dependent Claims (68, 69, 70, 71, 72, 73)
-
-
74. An information handling system comprising:
-
a processor; and a memory device coupled to the processor, the memory device comprising;
control circuitry; anddata input buffers configured in an off state, the data input buffers switchable to an on state responsive to the control circuitry detecting an externally generated command sequence of n cycles, wherein the control circuitry is configured to place the data input buffers in an on state in response to detecting a first m cycles of the command sequence of n cycles, wherein the control circuitry is further configured to detect a first m cycles of a command sequence of n cycles by determining the presence of at least one write command with a predetermined address in the first m cycles.
-
-
75. An apparatus comprising:
a control unit to write to a memory, the control unit configured to arrange a command sequence to control writing of data to the memory, the command sequence having n cycles such that the sequence of n cycles contains valid data for each cycle containing a write command beginning in a mth cycle, m<
n, wherein the command sequence contains arbitrary data for each cycle containing a write command prior to the mth cycle and the command sequence includes at least one cycle having a write command prior to the mth cycle, the arrangement of the command sequence to turn on a data input buffer in the memory and to write to the memory.- View Dependent Claims (76, 77, 78, 79, 80)
Specification