Method and system for capturing and bypassing memory transactions in a hub-based memory system
First Claim
1. A memory hub, comprising:
- a reception port coupled to a bypass path, the reception port operable to receive memory requests;
a memory controller coupled to the reception port, the reception port operable to concurrently supply a memory request to the bypass path and capture the memory request for supply to the memory controller; and
a transmission port coupled to the bypass path, the transmission port operable to receive memory requests from the reception port without going through the memory controller.
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Abstract
A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of the captured data words on an output in response to a second clock signal in a second time domain. A transmission interface is coupled to the reception interface to receive the captured data words and captures the data words in response to a third clock signal in the first time domain. This interface provides the captured data words on an output. Local control circuitry is coupled to the output of the reception interface to receive the groups of data words and develops memory requests corresponding to the groups of data words. The first clock domain is defined by clock signals having frequencies higher than frequencies of clock signals in the second clock domain.
288 Citations
31 Claims
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1. A memory hub, comprising:
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a reception port coupled to a bypass path, the reception port operable to receive memory requests; a memory controller coupled to the reception port, the reception port operable to concurrently supply a memory request to the bypass path and capture the memory request for supply to the memory controller; and a transmission port coupled to the bypass path, the transmission port operable to receive memory requests from the reception port without going through the memory controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory system, comprising:
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a system controller; a plurality of memory modules, each memory module coupled to adjacent memory module, at least one memory module being coupled to the system controller, each memory module comprising; a plurality of memory devices; a reception port coupled to a bypass path, the reception port operable to receive memory requests; a memory controller coupled to the reception port, the reception port operable to concurrently supply a memory request to the bypass path and capture the memory request for supply to the memory controller; and a transmission port coupled to the bypass path, the transmission port operable to receive memory requests from the reception port without going through the memory controller. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A computer system, comprising:
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a central processing unit; a system controller coupled to the central processing unit; an input device coupled to the system controller; an output device coupled to the system controller; a plurality of memory modules, each memory module coupled to adjacent memory module, at least one memory module being coupled to the system controller, each memory module comprising; a plurality of memory devices; a reception port coupled to a bypass path, the reception port operable to receive memory requests; a memory controller coupled to the reception port, the reception port operable to concurrently supply a memory request to the bypass path and capture the memory request for supply to the memory controller; and a transmission port coupled to the bypass path, the transmission port operable to receive memory requests from the reception port without going through the memory controller. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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24. A method of processing a memory request in a system memory, comprising:
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receiving a data word in a reception port of a memory hub; capturing the data word in the reception port for transmission to a memory controller; and concurrent with capturing the data word, transmitting the data word from the reception port to a transmission port without going through the memory controller. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31)
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Specification