Memory check architecture and method for a multiprocessor computer system
First Claim
1. In a multiprocessor computer system having a plurality of processing nodes coupled in an array wherein each processing node is coupled to at least one other processing node, and a memory distributed among the plurality of processing nodes, a method of testing the memory comprising the steps of:
- determining a configuration of the array;
determining an initial configuration of the memory,testing the memory over the array according to said initial configuration to identify a bad memory element;
communicating said initial configuration to each of the plurality of processing nodes before said step of testing; and
modifying said initial configuration to form a revised configuration that excludes said bad memory element.
1 Assignment
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Accused Products
Abstract
Methods and apparatus are provided for use in testing a memory (220, 230, 240) in a multiprocessor computer system (200). The multiprocessor computer system (200) has a plurality of processing nodes (210-217) coupled in an array wherein each processing node is coupled to at least one other processing node, and a memory (220, 230, 240) distributed among the plurality of processing nodes (210-217). A configuration of the array is determined. An initial configuration of the memory (220, 230, 240) is also determined. The memory (220, 230, 240) is tested over the array according to the initial configuration to identify a bad memory element. The initial configuration is modified to form a revised configuration that excludes the bad memory element.
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Citations
23 Claims
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1. In a multiprocessor computer system having a plurality of processing nodes coupled in an array wherein each processing node is coupled to at least one other processing node, and a memory distributed among the plurality of processing nodes, a method of testing the memory comprising the steps of:
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determining a configuration of the array; determining an initial configuration of the memory, testing the memory over the array according to said initial configuration to identify a bad memory element; communicating said initial configuration to each of the plurality of processing nodes before said step of testing; and modifying said initial configuration to form a revised configuration that excludes said bad memory element. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. In a multiprocessor computer system having a plurality of processing nodes and a memory distributed among the plurality of processing nodes, a method of testing the memory comprising the steps of:
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configuring the memory by programming the plurality of processing nodes with an initial configuration; testing the memory using said initial configuration to identify a bad memory element; determining a node and a region defined on said node which are associated with said bad memory element, wherein said step of determining said node and said region comprises the steps of, for successive ones of the plurality of processing nodes and until said region is found;
determining a last enabled region on a respective processing node, if any; and
determining whether a physical address of said bad memory element falls within said last enabled region;reconfiguring the memory by programming the plurality of processing nodes with a revised configuration that excludes said region; and operating the multiprocessor computer system using said revised configuration. - View Dependent Claims (9, 10, 11, 12, 13)
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14. For use in a multiprocessor computer system including:
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a plurality of processing nodes coupled in an array wherein each processing node is coupled to at least one other processing node; and a memory distributed among the plurality of processing nodes, a basic input/output system (BIOS) memory adapted to be coupled to one of the plurality of processing nodes, designated a boot strap processor (BSP), said BIOS memory comprising; a first set of instructions executable by said BSP to determine a configuration of the array; a second set of instructions executable by said BSP to determine an initial configuration of the memory and communicate said initial configuration to said plurality of processing nodes over the array; a third set of instructions executable by said BSP to test the memory over the array according to said initial configuration to identify a bad memory element; and a fourth set of instructions executable by said BSP to modify said initial configuration to form a revised configuration that excludes said bad memory element. - View Dependent Claims (15, 16, 17, 18)
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19. For use in a multiprocessor computer system including:
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a plurality of processing nodes coupled in an array wherein each processing node is coupled to at least one other processing node; and a memory distributed among the plurality of processing nodes, a basic input/output system (BIOS) memory adapted to be coupled to one of the plurality of processing nodes, designated a boot strap processor (BSP), said BIOS memory comprising; a first set of instructions executable by said BSP to configure the memory by programming the plurality of processing nodes with an initial configuration; a second set of instructions executable by said BSP to test the memory using said initial configuration to identify a bad memory element, wherein said second set of instructions further causes said boot strap processor to communicate said initial configuration to said plurality of processing nodes over the array; a third set of instructions executable by said BSP to determine a node and a region defined on said node which are associated with said bad memory element; a fourth set of instructions executable by said BSP to reconfigure the memory by programming the plurality of processing nodes with a revised configuration that excludes said region; and a fifth set of instructions executable by said BSP to operate the multiprocessor computer system using said revised configuration. - View Dependent Claims (20, 21, 22, 23)
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Specification