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Memory check architecture and method for a multiprocessor computer system

  • US 7,251,744 B1
  • Filed: 01/21/2004
  • Issued: 07/31/2007
  • Est. Priority Date: 01/21/2004
  • Status: Active Grant
First Claim
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1. In a multiprocessor computer system having a plurality of processing nodes coupled in an array wherein each processing node is coupled to at least one other processing node, and a memory distributed among the plurality of processing nodes, a method of testing the memory comprising the steps of:

  • determining a configuration of the array;

    determining an initial configuration of the memory,testing the memory over the array according to said initial configuration to identify a bad memory element;

    communicating said initial configuration to each of the plurality of processing nodes before said step of testing; and

    modifying said initial configuration to form a revised configuration that excludes said bad memory element.

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