Memory testing
First Claim
1. A structure, comprising:
- a BIST (Built-In-Self-Test) circuit; and
a first memory circuit electrically coupled to the BIST circuit, wherein the BIST circuit is configured to perform a first test pass for the first memory circuit to collect the cycle numbers of failing cycles for the first memory circuit in response to the first memory circuit being selected for testing, and wherein, during a second test pass for the first memory circuit performed by the BIST after the first test pass for the first memory circuit, the BIST circuit is configured to collect the contents of the locations in the first memory circuit associated with the failing cycles for the first memory circuit.
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Accused Products
Abstract
A structure comprising a memory chip and a tester for testing the memory chip, and a method for operating the structure. The memory chip comprises a BIST (Built-in Self Test) circuit, a plurality of RAMs (Random Access Memories). A first RAM is selected for testing by scanning in a select value into a RAM select register in the BIST. While the BIST performs a first testing pass for the first RAM, the tester collects cycle numbers of the failing cycles. Then, the BIST performs a second testing pass for the first RAM. At each failing cycle identified during the first testing pass, the BIST pauses so that the content of the location of the first RAM associated with the failing cycle and the state of the BIST can be extracted out of the memory chip. The testing procedures for the other RAMs are similar to that of the first RAM.
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Citations
24 Claims
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1. A structure, comprising:
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a BIST (Built-In-Self-Test) circuit; and a first memory circuit electrically coupled to the BIST circuit, wherein the BIST circuit is configured to perform a first test pass for the first memory circuit to collect the cycle numbers of failing cycles for the first memory circuit in response to the first memory circuit being selected for testing, and wherein, during a second test pass for the first memory circuit performed by the BIST after the first test pass for the first memory circuit, the BIST circuit is configured to collect the contents of the locations in the first memory circuit associated with the failing cycles for the first memory circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for testing a structure, the method comprising the steps of:
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providing in the structure a BIST (Built-In-Self-Test) circuit and a first memory circuit electrically coupled to the BIST circuit; using the BIST circuit to perform a first test pass for the first memory circuit to collect the cycle numbers of failing cycles for the first memory circuit in response to the first memory circuit being selected for testing; and after performing the first test pass for the first memory circuit, using the BIST circuit to perform a second test pass for the first memory circuit to collect the contents of the locations in the first memory circuit associated with the failing cycles for the first memory circuit. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for testing a memory chip, the method comprising the steps of:
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providing in the memory chip a RAM (Random Access Memory) and a BIST (Built-In-Self-Test) circuit; providing a RAM select register in the BIST circuit; scanning in a select value into the RAM select register so as to select the RAM for testing; using the BIST circuit to test the RAM for a first test pass to collect the cycle numbers of failing cycles in response to the RAM being selected for testing; and after testing the RAM for the first test pass, using the BIST circuit to test the RAM for a second test pass, wherein the second test pass comprises the same sequence of cycles as the first test pass, and wherein during the second test pass, the BIST circuit pauses at each failing cycle so that the contents of the locations of the RAIVI associated with the failing cycles can be extracted out of the memory chip. - View Dependent Claims (22, 23, 24)
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Specification