ASICs having more features than generally usable at one time and methods of use

• US 7,251,805 B2
• Filed: 10/12/2004
• Issued: 07/31/2007
• Est. Priority Date: 10/12/2004
• Status: Active Grant

• Current Assignee: Sheyu Group LLC (Intellectual Ventures LLC)
• Original Assignee: Nanotec Corporation
• Inventors: Koo, James T.
• Primary Examiner(s): Siek; Vuthe
• Application Number:
  US10/964,456
• Publication Number:
  US 20060080631A1
• Time in Patent Office: 1,022 Days
• Field of Search: 716/1, 716/16, 716/17, 713/171, 713/322, 713/324, 326 37- 39, 326/41, 326/47, 370/363
• US Class Current: 326/41
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different market spaces and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. In one embodiment, a mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a mass produced can quickly respond to shifting market demands.

Claims

1. A mega-ASIC comprising:

(a) an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads;

(b) an excess of ASIC functional blocks provided in said predefined circuit space, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuits, which if provided, are provided for recovering from spot manufacturing defects, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks,

wherein the excess and different I/O blocks include a first set of front-end I/O blocks and a second set of, back-end I/O blocks, and where the mega-ASIC further includes;

programmable, block activating/de-activating means capable of selectively activating one or more of the front-end I/O blocks and of selectively activating one or more of the back-end I/O blocks.

2. A mega-ASIC comprising:

(a) an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads;

(b) an excess of ASIC functional blocks provided in said predefined circuit space, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuits, which if provided, are provided for recovering from spot manufacturing defect, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks; and

(c) programmable, block activating/de-activating means capable of selectively activating a subset of one or more of said excess of ASIC functional blocks;

wherein;

(c.1) said programmable, block activating/de-activating means is operatively coupled to a buried bonding pad for receiving program data from the buried bonding pad.

3. A mega-ASIC comprising:

(a) an integrated circuit substrate having a predefined circuit space and a predefined number of bonding pads;

(b) an excess of ASIC functional blocks provided in said predefined circuit space, said excess including more ASIC functional blocks than can be operatively used at one time by the ASIC, the excess of ASIC functional blocks being defined to not count redundant defect-bypassing circuits, which if provided, are provided for recovering from spot manufacturing defects, where the excess ASIC functional blocks include different I/O blocks and/or different user-feature blocks; and

(c) programmable, block activating/de-activating means capable of selectively activating a subset of one or more of said excess of ASIC functional blocks;

wherein;

(c.1) said programmable, block activating/de-activating means is operatively coupled to a serial testing circuit for receiving program data from the serial testing circuit, and

(c.1a) said serial testing circuit includes decryption circuitry for receiving an encrypted key signal, where proper decryption of the encrypted key signal is required to enable the programmable, block activating/de-activating means to be programmed with configuration data.