Pillar cell flash memory technology

• US 7,253,055 B2
• Filed: 03/29/2006
• Issued: 08/07/2007
• Est. Priority Date: 12/10/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Lutze, Jeffrey W.
• Primary Examiner(s): Trinh; Michael
• Application Number:
  US11/277,907
• Publication Number:
  US 20060160305A1
• Time in Patent Office: 496 Days
• Field of Search: 438/257, 438/238, 438/259, 438/261, 438/264, 438/263
• US Class Current: 438/257
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).

Claims

1. A method of forming an array of erasable re-programmable non-volatile memory cells across at least a portion of a semiconductor substrate, comprising:

forming a first layer of dielectric across at least the array portion of a surface of the substrate,

forming a first layer of conductive material over the first dielectric layer across at least the array portion,

forming a second layer of dielectric material over the first conductive material layer,

forming a second layer of conductive material over the second dielectric layer,

anisotropically etching a first set of channels through the first and second layers of conductive material, the first and second layers of dielectric material and into the substrate surface to form trenches therein, said first set of channels and trenches being elongated in one direction across the array portion and spaced apart in a second direction across the array portion, the first and second directions being orthogonal with each other,

thereafter anisotropically etching a second set of channels through the first and second layers of conductive material, the first and second layers of dielectric material and into the substrate surface to form trenches therein, said second set of channels and trenches being elongated in the second direction across the array portion and spaced apart in the first direction across the array portion,

thereby to leave an array of pillars across the array portion surrounded by the first and second sets of channels and trenches, and

thereafter forming one set of conductors that extend across and contact the second layer of conductive material remaining as part of the pillars, said one set of conductors being elongated in the first direction and spaced apart in the second direction.

2. The method of claim 1, further comprising thereafter forming a second set of conductors that extend across said one set of conductors with dielectric therebetween, said second set of conductors being elongated in the second direction and spaced apart in the first direction.

3. The method of claim 2, wherein forming each of the one and second set of conductors includes extending said conductors into the channels between adjacent pillars to at least an extent that shields floating gates of adjacent pillars from each other in both the first and second directions.

4. The method of claim 2, further comprising, prior to forming the second set of conductors, implanting ions in the trenches at locations between at least some of the pillars along the second direction, thereby to form source and drain regions.

5. The method of claim 4, wherein forming the second set of conductors includes extending the second set of conductors into the trenches in positions between at least some the pillars along the second direction in which source and drain regions have not been formed and with dielectric therebetween, thereby to isolate floating gates of adjacent pillars from one another in the second direction and to serve as select transistor gates.

6. The method of claim 5, wherein forming said one set of conductors includes extending the one set of conductors into the channels between floating gates of adjacent pillars in the first direction, thereby to isolate floating gates of adjacent pillars from one another in the first direction.