Method of manufacturing semiconductor device that includes forming self-aligned contact pad

• US 7,253,099 B2
• Filed: 09/30/2004
• Issued: 08/07/2007
• Est. Priority Date: 11/08/2003
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jeong-Yun, Park, Yong-Hyeon, Kim, Tae-Ryong, Hwang, Jae-Hee
• Primary Examiner(s): Pham; Thanhha S.
• Application Number:
  US10/957,305
• Publication Number:
  US 20050101127A1
• Time in Patent Office: 1,041 Days
• Field of Search: 438229-230, 438/624, 438/634, 438637-640, 438734-735, 257/E21.24, 257/E21.577
• US Class Current: 438/637
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

According to some embodiments, a gate electrode structure including a gate electrode stack and a spacer, and source/drain region are formed on a semiconductor substrate. A first interlayer insulating layer having a thickness greater than that of the gate electrode structure is formed on the semiconductor substrate. On the first interlayer insulating layer, an etch inducing and focusing mask extending in a same direction as a length direction of the gate electrode structure and covering the gate electrode structure is formed. A second interlayer insulating layer is formed on the first interlayer insulating layer. A photoresist pattern is formed on the second interlayer insulating layer. The second interlayer insulating layer and the first interlayer insulating layer are sequentially etched using the photoresist pattern as an etch mask, thereby forming a SAC hole. A conductive material is used to fill in the SAC hole to form a SAC pad.

Claims

1. A method comprising:

forming a conductive line structure on a semiconductor substrate;

forming a first interlayer insulating layer on the semiconductor substrate, the first interlayer insulating layer having a thickness greater than that of the conductive line structure;

forming an etch inducing and focusing mask on the first interlayer insulating layer, the etch inducing and focusing mask extending in the same direction as a length direction of the conductive line structure and covering the conductive line structure;

forming a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer having a thickness that is equal to or greater than a thickness of the etch inducing and focusing mask;

forming a photoresist pattern on the second interlayer insulating layer;

etching the second interlayer insulating layer and the first interlayer insulating layer using the photoresist pattern as an etch mask to form a SAC hole, wherein the first interlayer insulating layer and the second interlayer insulating layer are selectively etched with respect to the etch inducing and focusing mask, said SAC hole exposing a portion of the conductive line structure and a portion of the semiconductor substrate adjacent to the conductive line structure; and

filling a conductive material in the SAC hole to form a SAC pad.

2. The method of claim 1, wherein the conductive line structure comprises a conductive line stack and a sidewall spacer, and the etch inducing and focusing mask has a width that is equal to or greater than a width of the conductive line stack.

3. The method of claim 2, wherein the conductive line stack comprises a conductive film and a hard mask, the hard mask having a thickness ranging from 500 Å

to 1,500 Å

.

4. The method of claim 2, wherein the etch inducing and focusing mask has a width that is greater than the width of the conductive line stack and is less than a sum of the width of the conductive line stack and a thickness of the sidewall spacer.

5. The method of claim 2, wherein a width of the etch inducing and focusing mask corresponds to a thickness of the shoulder of the conductive line structure and the height of the first interlayer insulating layer.

6. The method of claim 1, wherein a thickness of a shoulder of the conductive line structure ranges from 100 Å

to 350 Å

.

7. The method of claim 1, wherein the etch inducing and focusing mask is of a material having a high etch selectivity with respect to the first interlayer insulating layer and the second interlayer insulating layer.

8. The method of claim 1, wherein the etch inducing and focusing mask further comprises a middle bridge protecting pattern.

9. The method of claim 1, wherein the second interlayer insulating layer has a thickness less than a thickness of the etch inducing and focusing mask.

10. The method of claim 1, wherein forming the second interlayer insulating layer comprises forming a portion of the second interlayer insulating layer laterally adjacent to a sidewall of the etch inducing and focusing mask.

11. A method comprising:

preparing a semiconductor substrate on which an active region and a device isolation region are defined;

forming a gate electrode stack including a gate oxide film, a gate conductive film, and a hard mask on the semiconductor substrate;

forming a spacer on a sidewall of the gate electrode stack, thereby forming a gate electrode structure comprising the gate electrode stack and the spacer;

forming a source region and a drain region in the semiconductor substrate;

forming a first interlayer insulating layer on the semiconductor substrate, the first interlayer insulating layer having a thickness greater than that of the gate electrode structure;

forming an etch inducing and focusing mask on the first interlayer insulating layer, the etch inducing and focusing mask extending in a length direction of the gate electrode structure and covering the gate electrode stack;

forming a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer having a thickness that is equal to or greater than a thickness of the etch inducing and focusing mask;

forming a photoresist pattern on the second interlayer insulating layer;

sequentially etching the second interlayer insulating layer and the first interlayer insulating layer using the photoresist pattern as an etch mask to form a SAC hole exposing a portion of the gate electrode structure and a portion of the semiconductor substrate adjacent to the gate electrode structure, wherein the first interlayer insulating layer and the second interlayer insulating layer are selectively etched with respect to the etch inducing and focusing mask; and

filling a conductive material in the SAC hole to form a SAC pad.

12. The method of claim 11, wherein the hard mask has a thickness ranging from 500 Å

to 1,500 Å

.

13. The method of claim 11, wherein a thickness of a shoulder of the gate electrode structure ranges from 100 Å

to 350 Å

.

14. The method of claim 11, wherein the etch inducing and focusing mask has a width that is equal to or greater than a width of the gate electrode stack.

15. The method of claim 14, wherein the etch inducing and focusing mask has a width that is greater than the width of the gate electrode stack and is less than a sum of the width of the gate electrode stack and a thickness of the spacer.

16. The method of claim 14, wherein a width of the etch inducing and focusing mask corresponds to a thickness of the shoulder of the gate electrode structure and the thickness of the first interlayer insulating layer.

17. The method of claim 11, wherein the etch inducing and focusing mask is composed of a material having a high etch selectivity with respect to the first interlayer insulating layer and the second interlayer insulating layer.

18. The method of claim 11, wherein the etch inducing and focusing mask further comprises a middle bridge protecting pattern.

19. The method of claim 18, wherein forming the etch inducing and focusing mask includes forming a plurality of etch inducing and focusing masks on the first interlayer insulating layer, wherein the middle bridge protecting pattern connects adjacent etch inducing and focusing masks and is disposed in a space between the source region along a lengthwise direction of the gate electrode structure.

20. A method comprising:

forming a conductive line structure on a semiconductor substrate;

forming a first interlayer insulating layer on the semiconductor substrate, the first interlayer insulating layer having a thickness greater than that of the conductive line structure;

forming an etch inducing and focusing mask on the first interlayer insulating layer, the etch inducing and focusing mask extending in the same direction as a length direction of the conductive line structure and covering the conductive line structure;

forming a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer having a thickness that is equal to or greater than a thickness of the etch inducing and focusing mask;

forming a photoresist pattern on the second interlayer insulating layer;

etching the second interlayer insulating layer and the first interlayer insulating layer using the photoresist pattern as an etch mask to form a SAC hole exposing a shoulder of the conductive line structure and a portion of the semiconductor substrate adjacent to the conductive line structure, wherein the first interlayer insulating layer is selectively etched with respect to the etch inducing and focusing mask; and

filling a conductive material in the SAC hole to form a SAC pad.