Reliable BEOL integration process with direct CMP of porous SiCOH dielectric

• US 7,253,105 B2
• Filed: 02/22/2005
• Issued: 08/07/2007
• Est. Priority Date: 02/22/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Dimitrakopoulos, Christos D., Gates, Stephen M., Mehta, Sanjay C., McGahay, Vincent J.
• Primary Examiner(s): Geyer; Scott B.
• Assistant Examiner(s): Ullah; Elias
• Application Number:
  US11/063,152
• Publication Number:
  US 20060189133A1
• Time in Patent Office: 896 Days
• Field of Search: 438/622, 438/631, 438/674
• US Class Current: 438/674
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

Claims

1. A method of fabricating an interconnect structure comprising:

providing a structure comprising a porous ultra low k (ULK) dielectric having a dielectric constant of less than 3.0 on a substrate, said porous ULK dielectric having at least one opening located therein;

filling said at least one opening with at least a conductive material;

planarizing at least said conductive material utilizing a CMP slurry to provide a planarized structure having an upper surface of said conductive material that is substantially coplanar with an upper surface of said ULK dielectric, said ULK dielectric is exposed to said CMP slurry and said planarizing provides a planarized ULK dielectric with patterned conductors having a leakage current density that is lower than that measured without an UV radiation exposure step, and a breakdown field that is higher than that measured without an UV radiation exposure step;

exposing said planarized structure to UV radiation at a temperature from about 200°

to about 450°

C.;

subjecting said planarized structure to a plasma preclean process; and

forming a capping layer on at least said conductive material.

2. The method of claim 1 wherein said ULK dielectric is a dielectric material comprising atoms of Si, C, O and H that are bonded in a tri-dimensional network structure.

3. The method of claim 2 wherein said ULK dielectric is formed by deposition and curing.

4. The method of claim 3 wherein said ULK dielectric has about 50% or less of porogen remaining after said curing.

5. The method of claim 1 wherein said ULK dielectric is formed by providing at least a first precursor comprising atoms of Si, C, O and H and an inert gas into a reactor, and then depositing said ULK dielectric using said first precursor.

6. The method of claim 1 wherein said planarizing step causes Si—

OH groups to be formed in said ULK dielectric which increase the dielectric constant of said ULK dielectric.

7. The method of claim 1 wherein said temperature of said UV exposure is about 400°

C.

8. The method of claim 1 wherein said UV exposure is performed utilizing a source that can generate a light having a wavelength from about 150 to about 500 nm.

9. The method of claim 1 wherein said UV exposure is performed in the presence of an inert gas that can be optionally mixed with a chemically active species.

10. The method of claim 9 wherein said chemically active species is one of H₂, CH₄, trimethylsilane, ethylene or a silane derivative of the formula HSiRR₁R₂ wherein R, R₁ and R₂ may be the same or different and are selected from group consisting of methyl, ethyl, propyl, vinyl, allyl, methoxy and ethoxy.

11. The method of claim 1 wherein a gradient surface layer having a density gradient and a C content gradient is formed on said ULK dielectric during said exposing step.

12. The method of claim 1 wherein said plasma precleaning process is performed at a temperature from about 350°

to about 450°

C. in a nitrogen-containing plasma.

13. The method of claim 1 further comprising performing an additional UV exposure step following formation of said capping layer.

14. The method of claim 13 wherein said additional UV exposure removes damage caused by said plasma precleaning process.

15. The method of claim 1 wherein said exposing said planarized structure to UV radiation is replaced by a step of forming a hydrophobic surface on said ULK dielectric.

16. The method of claim 15 wherein forming said hydrophobic surface comprises a step of contacting said ULK dielectric with a silylating agent.

17. The method of claim 1 wherein said steps of providing a structure, filling, planarizing, exposing, subjecting and forming a capping layer are repeated from 2 to 10 times.

18. The method of claim 1 wherein said steps of planarizing and exposing provide an ULK dielectric having a gradient surface layer, said planarized and exposed ULK dielectric having an electrical leakage current density at a field of 1-2 MV/cm of less than about 10E-7 Amp/cm² and a breakdown field of about 5 MV/cm or greater.

19. A method of fabricating an interconnect structure comprising:

providing a structure comprising a porous ultra low k (ULK) dielectric having a dielectric constant of less than 3.0 on a substrate and at least one opening located therein, said porous ULK dielectric is formed by deposition and curing and having about 50% or less of porogen after said curing;

filling said at least one opening with at least a conductive material;

planarizing at least said conductive material utilizing a CMP slurry to provide a planarized structure having an upper surface of said conductive material that is substantially coplanar with an upper surface of said ULK dielectric, said ULK dielectric is exposed to said CMP;

exposing said planarized structure to UV radiation at a temperature from about 200°

to about 450°

C.;

subjecting said planarized structure to a plasma preclean process; and

forming a capping layer on at least said conductive material.

20. A method of fabricating an interconnect structure comprising:

providing a structure comprising a porous ultra low k (ULK) dielectric having a dielectric constant of less than 3.0 on a substrate, said porous ULK dielectric having at least one opening located therein, and said porous ULK dielectric is formed by providing at least a first precursor comprising atoms of Si, C, O and H and an inert gas into a reactor, depositing said ULK dielectric using said first precursor and thereafter curing;

filling said at least one opening with at least a conductive material;

planarizing at least said conductive material utilizing a CMP slurry to provide a planarized structure having an upper surface of said conductive material that is substantially coplanar with an upper surface of said ULK dielectric, said ULK dielectric is exposed to said CMP slurry;

exposing said planarized structure to UV radiation at a temperature from about 200°

to about 450°

C.;

subjecting said planarized structure to a plasma preclean process; and

forming a capping layer on at least said conductive material.