Chip packaging structure having redistribution layer with recess

• US 7,253,519 B2
• Filed: 06/09/2004
• Issued: 08/07/2007
• Est. Priority Date: 06/09/2003
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Huang, Min-Lung, Weng, Chao-Fu, Su, Ching-Huei, Tsai, Chi-Long
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US10/709,953
• Publication Number:
  US 20040245630A1
• Time in Patent Office: 1,154 Days
• Field of Search: 257/E23.069, 257/E23.021, 257/E23.02, 257/E23.179, 257/737, 257/734, 257/738, 257/700, 257/701, 257/758, 257781-783, 257772-774, 257/779, 257/780, 257/761, 257763-766
• US Class Current: 257/738
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02351 comprising interlocking features
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05172 Vanadium [V] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN

Abstract

A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. The redistribution layer is formed over the first passivation layer and electrically connected to the bonding pad. Furthermore, the redistribution layer also extends from the bonding pad to the recess. The second passivation layer is formed over the first passivation layer and the redistribution layer. The second passivation layer also has an opening that exposes the redistribution layer above the recess. The bump passes through the opening and connects electrically with the redistribution layer above the recess.

Claims

1. A chip packaging structure, comprising:

a chip having a first passivation layer and at least a bonding pad, wherein the bonding pad is exposed by the first passivation layer and the first passivation layer has at least a recess, the whole recess has a sidewall and a bottom surface being exposed;

a redistribution layer formed over the first passivation layer, wherein the redistribution layer electrically connects with the bonding pad and extends from the bonding pad to the recess, and in contact with the sidewall and the bottom surface of the recess and the redistribution layer further comprises;

a first metallic layer formed over the first passivation layer, wherein a material constituting the first metallic layer is selected from the group consisting of aluminum, titanium, titanium-tungsten alloy, tantalum, tantalum nitride and chromium;

a second metallic layer formed over the first metallic layer; and

a third metallic layer formed over the second metallic layer;

a second passivation layer formed over the first passivation layer and the redistribution layer, wherein the second passivation layer has an opening that exposes the redistribution layer above the recess; and

at least a bump disposed inside the opening and electrically connected to the redistribution layer above the recess.

2. The chip packaging structure of claim 1, wherein the recess has an obtuse angle and is formed between the sidewall of the recess and the bottom surface of the recess.

3. The chip packaging structure of claim 1, further comprising at least an under-bump-metallurgy layer formed in the opening of the second passivation layer and extending over an upper surface of the second passivation layer, wherein the hump is on the under-bump-metallurgy layer and electrically connected to the redistribution layer above the recess.

4. The chip structure of claim 3, wherein the under-bump-metallurgy layer further comprises:

a first metallic layer formed over the opening-exposed redistribution layer; and

a second metallic layer formed over the first metallic layer.

5. The chip structure of claim 4, wherein a material constituting the first metallic layer is selected from the group consisting of aluminum, titanium, titanium-tungsten alloy, tantalum, tantalum nitride and chromium.

6. The chip structure of claim 4, wherein a material constituting the second metallic layer comprises copper.

7. The chip structure of claim 4, wherein the under-bump-metallurgy layer further comprises at least an electroplated layer formed over the second metallic layer and the electroplated layer is selected from the group consisting of an electroplated copper layer, an electroplated nickel layer, an electroless nickel layer, an electroless plated gold layer and combination thereof.

8. The chip packaging structure of claim 3, wherein the under-bump-metallurgy layer further comprises:

a first metallic layer formed over the opening-exposed redistribution layer;

a second metallic layer formed over the first metallic layer; and

a third metallic layer formed over the second metallic layer.

9. The chip packaging structure or claim 8, wherein a material constituting the first metallic layer is selected from the group consisting of aluminum, titanium, titanium-tungsten alloy, tantalum, tantalum nitride and chromium.

10. The chip packaging structure of claim 8, wherein a material constituting the second metallic layer is selected from the group consisting of nickel-vanadium alloy and copper-chromium alloy.

11. The chip packaging structure of claim 8, wherein a material constituting the third metallic layer comprises copper.

12. The chip packaging structure of claim 8, wherein the under-bump-metallurgy layer further comprises at least an electroplated layer formed over the third metallic layer and the electroplated layer is selected from the group consisting of an electroplated copper layer, an electroplated nickel layer, an electroplated gold layer and combination thereof.

13. The chip packaging structure of claim 1, wherein a material constituting the second metallic layer comprises copper.

16. The chip packaging structure of claim 1, wherein an obtuse angle is formed between a sidewall of the opening and a bottom surface of the opening.

14. A chip packaging structure, comprising:

a chip haying a first passivation layer and at least a bonding pad, wherein the bonding pad is exposed by the first passivation layer and the first passivation layer has at least a recess, the whole recess has a sidewall and a bottom surface being exposed;

a redistribution layer formed over the first passivation layer, wherein the redistribution layer electrically connects with the bonding pad and extends from the bonding, pad to the recess, and in contact with the sidewall and the bottom surface of the recess and the redistribution layer further comprises;

a first metallic layer formed over the first passivation layer;

a second metallic layer formed over the first metallic layer, wherein a material constituting the second metallic layer is selected from the group consisting of nickel-vanadium alloy and copper-chromium alloy, and

a third metallic layer formed over the second metallic layer;

a second passivation layer formed over the first passivation layer and the redistribution layer, wherein the second passivation layer has an opening that exposes the redistribution layer above the recess; and

at least a bump disposed inside the opening and electrically connected to the redistribution layer above the recess.

15. The chip packaging structure of claim 14, wherein a material constituting the third metallic layer comprises copper.

17. The chip packaging structure of claim 14, wherein the recess has an obtuse angle and is formed between the sidewall of the recess and the bottom surface of the recess.

18. The chip packaging structure of claim 14, further comprising at least an under-bump-metallurgy layer formed in the opening of the second passivation layer and extending over an upper surface of the second passivation layer, wherein the bump is on the under-bump-metallurgy layer and electrically connected to the redistribution layer above the recess.