Method for producing chip stacks

• US 7,253,530 B2
• Filed: 09/26/2005
• Issued: 08/07/2007
• Est. Priority Date: 03/24/2003
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hubner, Holger
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US11/236,311
• Publication Number:
  US 20060055051A1
• Time in Patent Office: 680 Days
• Field of Search: None
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/83825 Solid-liquid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01068 Erbium [Er]

Abstract

A plurality of interconnect layers are produced on a top side of one or two semiconductor chips, and are mutually isolated from one another in each case by insulation layers that are patterned in such a way that an interconnect layer applied as bridge makes contact with the interconnects applied previously.

Claims

1. A method for producing chip stacks, comprising the steps of:

providing a first semiconductor chip with first contact areas in a metal layer covered with an electrically insulating layer;

producing at least two plated-through holes to at least two of said first contact areas, respectively, and first interconnects are respectively connected to the at least two plated-through holes;

providing a second semiconductor chip with a second contact area in a metal layer covered with an electrically insulating layer;

producing a plated-through hole to the second contact area with a second interconnect connected to the plated-through hole;

producing a third interconnect to be bridged on a top side of the first semiconductor chip which has the first interconnect;

applying an insulation layer covering the first and third interconnects of the first semiconductor chip, which insulation layer is provided with openings on respective top sides of the first interconnects to be connected;

applying at least one fourth interconnect, which contacts the first interconnects to be connected, in the relevant openings of the insulation layer;

arranging the first semiconductor chip and the second semiconductor chip to be opposite one another such that the first and second interconnects lie on top of one another; and

permanently electrically conductively connecting the first and second interconnects to one another by means of diffusion soldering using a solder layer applied to at least one of the first and second interconnects that are respectively to be connected to one another.

2. The method as claimed in claim 1, wherein the fourth interconnect is applied by electrodeposition with a thickness of less than 1 μ

m.

3. The method as claimed in claim 1, wherein prior to the application of the fourth interconnect, performing the step of applying a base layer for a purpose of improving subsequent deposition.

4. The method as claimed in claim 1, wherein the insulation layer is a polyimide that can be patterned photolithographically.

6. The method as claimed in claim 4, wherein the insulation covering is a polyimide that can be patterned photolithographically.

5. A method for producing chip stacks, comprising the steps of:

providing a first semiconductor chip with first contact areas in a metal layer covered with an electrically insulating layer;

producing at least two plated-through holes to at least two of said first contact areas, respectively, and first interconnects are respectively connected to the at least two plated-through holes;

providing a second semiconductor chip with a second contact area in a metal layer covered with an electrically insulating layer;

producing a plated-through hole to the second contact area with a second interconnect connected to the plated-through hole;

applying a solder layer to the second interconnect of the second semiconductor chip;

producing a third interconnect to be bridged on a top side of the first semiconductor chip which has the first interconnects;

applying an insulation covering that covers the third interconnect of the first semiconductor chip, wherein the insulation covering has an upper portion having a smaller thickness than the solder layer;

arranging the first semiconductor chip and the second semiconductor chip to be opposite one another such that the first and second interconnects lie on top of one another;

permanently electrically conductively connecting the interconnects to one another by means of diffusion soldering; and

during the connection of the semiconductor chips, displacing the solder layer between the third interconnect of the first semiconductor chip and the second interconnect of the second semiconductor chip.

7. A method for producing chip stacks, comprising the steps of:

producing a plurality of first interconnect layers on a top side of a first semiconductor chip;

producing a plurality of second interconnect layers on a top side of a second semiconductor chip;

applying and patterning insulation layers such that the interconnect layers of the first and second semiconductor chips are mutually isolated from one another;

applying a further interconnect layer as a bridge to contact with the first interconnect layers;

arranging the first semiconductor chip and the second semiconductor chip to be opposite one another such that the first and second interconnects lie on top of one another; and

permanently electrically conductively connecting the first and second interconnects to one another by means of diffusion soldering using a solder layer applied to at least one of the first and second interconnects that are respectively to be connected to one another.

8. A method for producing chip stacks, comprising the steps of:

producing a plurality of first interconnect layers on a top side of a first semiconductor chip;

producing a plurality of second interconnect layers on a top side of a second semiconductor chip;

applying and patterning insulation layers such that the interconnect layers of the first and second semiconductor chips are mutually isolated from one another;

applying a further interconnect layer as a bridge to contact with the first interconnect layers;

applying a solder layer to the second interconnect of the second semiconductor chip;

arranging the first semiconductor chip and the second semiconductor chip to be opposite one another such that the first and second interconnects lie on top of one another;

permanently electrically conductively connecting the interconnects to one another by means of diffusion soldering; and

during the connection of the semiconductor chips, displacing the solder layer between the third interconnect of the first semiconductor chip and the second interconnect of the second semiconductor chip.

9. A chip stack comprising:

a first semiconductor chip with first contact areas in a metal layer covered with an electrically insulating layer;

at least two plated-through holes connected to at least two of said first contact areas, respectively, and first interconnects respectively connected to the at least two plated-through holes;

a second semiconductor chip with a second contact area in a metal layer covered with an electrically insulating layer;

a plated-through hole connected to the second contact area with a second interconnect connected to the plated-through hole;

a third interconnect bridged on a top side of the first semiconductor chip which has the first interconnect;

an insulation layer covering the first and third interconnects on the first semiconductor chip, which insulation layer is provided with a respective opening on a respective top side of the first and having third interconnects to be connected; and

at least one fourth interconnect, which contacts the first interconnect to be connected, in the relevant openings of the insulation layer,

wherein the first semiconductor chip and the second semiconductor chip are arranged to be opposite one another such that the first and second interconnects lie on top of one another, and

wherein the first and second interconnects are permanently electrically conductively connecting to one another by means of diffusion soldering using a solder layer applied to at least one of the first and second interconnects that are respectively to be connected to one another.

10. A chip stack comprising:

a first semiconductor chip with first contact areas in a metal layer covered with an electrically insulating layer;

at least two plated-through holes connected to at least two of said first contact areas, respectively, and first interconnects are respectively connected to the at least two plated-through holes;

a second semiconductor chip with a second contact area in a metal layer covered with an electrically insulating layer;

a plated-through hole connected to the second contact area with a second interconnect connected to the plated-through hole;

a solder layer applied to the second interconnect of the second semiconductor chip;

a third interconnect bridged on a top side of the first semiconductor chip which has the first interconnects;

an insulation covering that covers the third interconnect to the first semiconductor chip, wherein the insulation covering has an upper portion having a smaller thickness than the solder layer; and

wherein the first semiconductor chip and the second semiconductor chip are arranged to be opposite one another such that the first and second interconnects lie on top of one another,

wherein the interconnects are permanently electrically conductively connected to one another by means of diffusion soldering; and

wherein during the connection of the semiconductor chips, the solder layer between the third interconnect of the first semiconductor chip and the second interconnect of the second semiconductor chip is displaced.