Differential amplifiers with enhanced gain and dynamic range

• US 7,253,686 B2
• Filed: 07/27/2005
• Issued: 08/07/2007
• Est. Priority Date: 07/27/2005
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Ali, Ahmed Mohamed Abdelatty
• Primary Examiner(s): NGUYEN, KHANH V
• Application Number:
  US11/191,871
• Publication Number:
  US 20070024368A1
• Time in Patent Office: 741 Days
• Field of Search: 330/253, 330/258, 330/259, 330/290
• US Class Current: 330/259
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 2203/45288 Differential amplifier with circuit arrangements to enhance the transconductance
• CPC Class Codes: H03F 2203/45301 there are multiple cascaded folded or not folded common gate stages of a cascode dif amp
• CPC Class Codes: H03F 2203/45311 the common gate stage of a cascode dif amp being implemented by multiple transistors
• CPC Class Codes: H03F 2203/45652 the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
• CPC Class Codes: H03F 2203/45722 the LC comprising one or more source followers, as post buffer or driver stages, in cascade in the LC
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03F 3/45286 Non-folded cascode stages
• CPC Class Codes: H03F 3/45291 Folded cascode stages
• CPC Class Codes: H03F 3/4565 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03F 3/45798 Controlling the common source circuit of the differential amplifier

Abstract

Differential amplifier embodiments are provided for amplifying input signals with enhanced gain and dynamic range. They include first and second amplifier stages and at least one common-mode feedback circuit that is arranged to mirror and adjust a tail current to control the common-mode level of a respective one of the stages. The stages are configured with cascode elements to obtain high impedances that enhance their signal gain and the common-mode feedback circuit is configured to controllably lower the output voltage of a current source that provides the tail current to thereby enhance the amplifier'"'"'s dynamic range. The amplifier embodiments are particularly suited for use in applications where they must operate with reduced supply voltages and operate in alternating operational modes.

Claims

1. An amplifier that processes signals from an amplifier input port to an amplifier output port, comprising:

a first differential pair of transistors that define said amplifier input port and a first differential port and are coupled to steer a first tail current across said first differential port in response to signals at said amplifier input port;

a second differential pair of transistors that define a second differential port for receiving signals from said first differential port and that define said amplifier output port and are coupled to steer a second tail current across said amplifier output port in response to signals at said second differential port; and

at least one feedback circuit arranged to mirror and adjust at least one of said first and second tail currents in response to signals from at least one of said second differential port and said amplifier output port;

wherein said feedback circuit includes;

a current source;

a reference generator that provides a reference signal;

a feedback amplifier configured to mirror said first tail current from said current source to said first differential pair and provide an error signal to adjust said first tail current in response to a difference between said reference signal and a common-mode signal at said second differential port.

2. The amplifier of claim 1, further including transistor followers inserted between said first and second differential ports to pass signals from said first differential port to said second differential port.

3. The amplifier of claim 1, wherein said feedback amplifier includes:

a replica transistor; and

a compression transistor coupled between a control terminal and a current terminal of said replica transistor with said control terminal coupled to mirror said first tail current from said current source.

4. The amplifier of claim 3, wherein said compression transistor has a control terminal which receives a reference voltage that approximates a common-mode level at said amplifier input port.

5. The amplifier of claim 1, wherein said reference generator includes:

a replica transistor;

a compression transistor coupled between a control terminal and a current terminal of said replica transistor; and

a diode-coupled transistor coupled to said control terminal to provide said reference signal.

6. The amplifier of claim 1, further including:

a current-source transistor coupled to provide said first tail current in response to said error signal;

a set of mode switches inserted to couple said feedback amplifier to said current-source transistor and said second differential port in selected ones of operational modes; and

signal-holding capacitors coupled between said current-source transistor and said first differential port.

7. The amplifier of claim 1, further including:

bipolar cascode transistors inserted into said first differential port to increase its output impedance;

current-source transistors positioned to provide currents to said first differential pair; and

at least one set of cascode transistors inserted between said bipolar cascode transistors and said current-source transistors to further increase impedance at said first differential port.

8. An amplifier that processes signals from an amplifier input port to an amplifier output port, comprising:

a first differential pair of transistors that define said amplifier input port and a first differential port and are coupled to steer a first tail current across said first differential port in response to signals at said amplifier input port;

a second differential pair of transistors that define a second differential port for receiving signals from said first differential port and that define said amplifier output port and are coupled to steer a second tail current across said amplifier output port in response to signals at said second differential port; and

at least one feedback circuit arranged to mirror and adjust at least one of said first and second tail currents in response to signals from at least one of said second differential port and said amplifier output port;

wherein said feedback circuit includes;

a current source;

a reference generator that provides a reference signal;

a feedback amplifier configured to mirror said second tail current from said current source to said second differential pair and provide an error signal to adjust said second tail current in response to a difference between said reference signal and a common-mode signal at said amplifier output port.

9. The amplifier of claim 8, further including transistor followers inserted between said first and second differential ports to pass signals from said first differential port to said second differential port.

10. The amplifier of claim 8, wherein said feedback amplifier includes:

a replica transistor; and

a compression transistor coupled between a control terminal and a current terminal of said replica transistor with said control terminal coupled to mirror said second tail current from said current source.

11. The amplifier of claim 10, wherein said compression transistor has a control terminal which receives a reference voltage that approximates a common-mode level at said second differential port.

12. The amplifier of claim 8, wherein said reference generator comprises a voltage divider that provides said reference signal.

13. The amplifier of claim 8, further including:

a current-source transistor coupled to provide said second tail current in response to said error signal;

a set of mode switches inserted to couple said feedback amplifier to said current-source transistor and said amplifier output port in selected ones of operational modes; and

signal-holding capacitors coupled between said current-source transistor and said amplifier output port.

14. The amplifier of claim 8, further including current-source transistors positioned to provide currents to said second differential pair, and

at least one set of cascode transistors inserted between said second differential pair and said current-source transistors to increase impedance at said amplifier output port.

15. An amplifier that processes signals from an amplifier input port to an amplifier output port, comprising:

a first current source

a first differential pair of transistors that define said amplifier input port and a first differential port and are coupled to steer a first tail current across said first differential port in response to signals at said amplifier input port;

first current-source transistors biased to provide currents;

two sets of cascode transistors inserted to couple said first current-source transistors to said first differential port;

a second current source

a second differential pair of transistors that define a second differential port for receiving signals from said first differential port and that define said amplifier output port and are coupled to steer a second tail current across said amplifier output port in response to signals at said second differential port;

second current-source transistors biased to provide currents;

a set of cascode transistors inserted to couple said second current-source transistors to said amplifier output port;

a first feedback circuit arranged to mirror said first tail current from said first current source and adjust said first tail current in response to signals from said second differential port; and

a second feedback circuit arranged to mirror said second tail current from said second current source and to adjust said second tail current in response to signals from said second differential port.

16. The amplifier of claim 15, further including transistor followers inserted between said first and second differential ports to pass signals from said first differential port to said second differential port and wherein said first feedback circuit includes:

a first reference generator that provides a first reference signal; and

a first feedback amplifier configured to mirror and adjust said first tail current in response to a difference between said first reference signal and a common-mode signal at said second differential port;

and wherein said second feedback circuit includes;

a second reference generator that provides a second reference signal; and

a second feedback amplifier configured to mirror and adjust said second tail current in response to a difference between said second reference signal and a common-mode signal at said amplifier output port.

17. The amplifier of claim 16, further including:

a third current-source transistor coupled to provide said first tail current in response to said first feedback circuit;

a first set of mode switches inserted to couple said first feedback amplifier to said third current-source transistor and said second differential port in selected ones of operational modes;

a fourth current-source transistor coupled to provide said second tail current in response to said second feedback circuit;

a second set of mode switches inserted to couple said second feedback amplifier to said fourth current-source transistor and said amplifier output port in selected ones of said operational modes; and

signal-holding capacitors coupled between said third current-source transistor and said first differential port and between said fourth current-source transistor and said second differential port.

18. A signal converter system for converting an analog input signal into a corresponding digital code, the system comprising:

at least two converter stages coupled in series to receive said analog input signal and each convert a respective portion of said analog input signal into a respective code portion of said digital code wherein at least one of said stages includes;

an analog-to-digital converter that provides that stage'"'"'s code portion and a selected one of a set of reference signals; and

a switched-capacitor network that generates the respective portion of a succeeding one of said converter stages with the aid of a differential amplifier that processes signals from an amplifier input port to an amplifier output port and includes;

a) a first current source;

b) a first differential pair of transistors that define said amplifier input port and a first differential port and are coupled to steer a first tail current across said first differential port in response to signals at said amplifier input port;

c) a second current source;

d) a second differential pair of transistors that define a second differential port for receiving signals from said first differential port and that define said amplifier output port and are coupled to steer a second tail current across said amplifier output port in response to signals at said second differential port; and

e) a first feedback circuit arranged to mirror said first tail current from said first current source and adjust said first tail current in response to signals from said second differential port; and

f) a second feedback circuit arranged to mirror said second tail current from said second current source and to adjust said second tail current in response to signals from said second differential port.

19. The system of claim 18, further including transistor followers inserted between said first and second differential ports to pass signals from said first differential port to said second differential port and wherein said first feedback circuit includes:

a first reference generator that provides a first reference signal; and

a first feedback amplifier configured to adjust said first tail current in response to a difference between said first reference signal and a common-mode signal at said second differential port;

and wherein said second feedback circuit includes;

a second reference generator that provides a second reference signal; and

a second feedback amplifier configured to adjust said second tail current in response to a difference between said second reference signal and a common-mode signal at said amplifier output port.

20. The system of claim 19, further including a third current-source transistor coupled to provide said first tail current in response to said first feedback circuit;

a first set of mode switches inserted to couple said first feedback amplifier to said third current-source transistor and said second differential port in selected ones of operational modes;

a fourth current-source transistor coupled to provide said second tail current in response to said second feedback circuit;

a second set of mode switches inserted to couple said second feedback amplifier to said fourth current-source transistor and said amplifier output port in selected ones of said operational modes; and

signal-holding capacitors coupled between said third current-source transistor and said first differential port and between said fourth current-source transistor and said second differential port.