Reference voltage generating circuit

• US 7,253,764 B2
• Filed: 08/08/2006
• Issued: 08/07/2007
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Liu, Chang-Shun, Wang, Wen-Chi, Lee, Chao-Cheng, Tsai, Jui-Yuan
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US11/463,014
• Publication Number:
  US 20070046523A1
• Time in Patent Office: 364 Days
• Field of Search: 341/172, 341/143, 341/150
• US Class Current: 341/172
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 3/464 Details of the digital/analogue conversion in the feedback path
• CPC Class Codes: H03M 3/502 Details of the final digital/analogue conversion following the digital delta-sigma modulation

Abstract

A reference voltage generating circuit includes: a first capacitor; a second capacitor; a reference voltage sampling capacitor; a first switch for alternatively coupling the second capacitor to a predetermined voltage to allow the second capacitor to sample the predetermined voltage; a second switch for alternatively coupling the second capacitor to the first capacitor to allow the second capacitor to redistribute charges with the first capacitor in order to generate the reference voltage; and a third switch for alternatively coupling the first capacitor to the reference voltage sampling capacitor to allow the reference voltage sampling capacitor to redistribute charges with the first capacitor in order to output the reference voltage.

Claims

1. A reference voltage generating circuit for generating a reference voltage according to a predetermined voltage, the reference voltage generating circuit comprising:

a first capacitor;

a second capacitor;

a reference voltage sampling capacitor;

a first switch, for alternatively coupling the second capacitor to the predetermined voltage, wherein the first switch couples the second capacitor to the predetermined voltage in a first stage such that the second capacitor samples the predetermined voltage;

a second switch, for alternatively coupling the second capacitor to the first capacitor, wherein the second switch couples the second capacitor to the first capacitor in a second stage in order to generate the reference voltage; and

a third switch, for alternatively coupling the first capacitor to the reference voltage sampling capacitor, wherein the third switch couples the first capacitor to the reference voltage sampling capacitor in the first stage such that the reference voltage sampling capacitor redistributes charges with the first capacitor to generate the reference voltage.

2. The reference voltage generating circuit of claim 1, wherein the first switch and the third switch are both controlled by a same clock.

3. The reference voltage generating circuit of claim 1, wherein the reference voltage generating circuit receives the predetermined voltage and filters the predetermined voltage to output the reference voltage.

4. The reference voltage generating circuit of claim 1, wherein the first switch breaks the electrical connection between the second capacitor and the predetermined voltage in the second stage.

5. The reference voltage generating circuit of claim 1, wherein the second capacitor redistributes charges with the first capacitor to generate the reference voltage.

6. The reference voltage generating circuit of claim 1, wherein the second switch breaks the electrical connection between the first capacitor and the second capacitor in the first stage.

7. The reference voltage generating circuit of claim 1, wherein the third switch breaks the electrical connection between the first capacitor and the reference voltage sampling capacitor in the second stage.

8. A sigma-delta analog-to-digital converter (ADC) comprising:

a reference voltage generating circuit, for generating a reference voltage according to a predetermined voltage, the reference voltage generating circuit comprising;

a first capacitor;

a second capacitor;

a reference voltage sampling capacitor;

a first switch, for alternatively coupling the second capacitor to the predetermined voltage, wherein the first switch couples the second capacitor to the predetermined voltage in a first stage such that the second capacitor samples the predetermined voltage;

a second switch, for alternatively coupling the second capacitor to the first capacitor, wherein the second switch couples the second capacitor to the first capacitor in the second stage such that the second capacitor redistributes charges with the first capacitor in order to generate the reference voltage; and

a third switch, for alternatively coupling the first capacitor to the reference voltage sampling capacitor, wherein the third switch couples the first capacitor to the reference voltage sampling capacitor in the first stage such that the reference voltage sampling capacitor redistributes charges with the first capacitor to generate the reference voltage; and

a sigma delta modulator, for receiving the reference voltage from the reference voltage sampling capacitor in the first stage and receiving an analog signal in the second stage in order to generate a corresponding digital signal according to the analog signal and the reference voltage.

9. The sigma-delta analog-to-digital converter (ADC) of claim 8, wherein the first switch and the third switch are both controlled by a first clock.

10. The sigma-delta analog-to-digital converter (ADC) of claim 9, wherein the second switch is controlled by a second clock.

11. The sigma-delta analog-to-digital converter (ADC) of claim 10, wherein the sigma delta modulator is controlled by the first clock and the second clock.

12. The sigma-delta analog-to-digital converter (ADC) of claim 8, wherein the reference voltage generating circuit receives the predetermined voltage and filters the predetermined voltage in order to generate the reference voltage.

13. The sigma-delta analog-to-digital converter (ADC) of claim 8, wherein the first switch breaks the electrical connection between the second capacitor and the predetermined voltage in the second stage.

14. The sigma-delta analog-to-digital converter (ADC) of claim 8, wherein the second capacitor redistributes charges with the first capacitor to generate the reference voltage.

15. The sigma-delta analog-to-digital converter (ADC) of claim 8, wherein the second switch breaks the electrical connection between the first capacitor and the second capacitor in the first stage.

16. The sigma-delta analog-to-digital converter (ADC) of claim 8, wherein the third switch breaks the electrical connection between the first capacitor and the reference voltage sampling capacitor in the second stage.

17. A sigma delta digital-to-analog converter (DAC) comprising:

a reference voltage generating circuit, for receiving a predetermined voltage and filtering the predetermined voltage to generate a reference voltage, the reference voltage generating circuit comprising;

a first capacitor;

a second capacitor;

a reference voltage sampling capacitor;

a first switch, for alternatively coupling the second capacitor to the predetermined voltage, wherein the first switch couples the second capacitor to the predetermined voltage in a first stage such that the second capacitor samples the predetermined voltage and breaks the electrical connection between the second capacitor and the predetermined voltage in a second stage;

a second switch, for alternatively coupling the second capacitor to the first capacitor, wherein the second switch couples the second capacitor to the first capacitor in the second stage such that the second capacitor redistributes charges with the first capacitor in order to generate the reference voltage and breaks the electrical connection between the first capacitor and the second capacitor in the first stage; and

a third switch, for alternatively coupling the first capacitor to the reference voltage sampling capacitor, wherein the third switch couples the first capacitor to the reference voltage sampling capacitor in the first stage such that the reference voltage sampling capacitor redistributes charges with the first capacitor to generate the reference voltage and breaks the electrical connection between the first capacitor and the reference voltage sampling capacitor in the second stage; and

a sigma delta modulator, for receiving the reference voltage from the reference voltage sampling capacitor according to a digital signal in the first stage to generate an analog signal.

18. The sigma delta digital-to-analog converter (DAC) of claim 17, wherein the first switch and the third switch are both controlled by a first clock, the second switch is controlled by a second clock, and the sigma-delta modulator is simultaneously controlled by the first clock and the second clock.

19. A reference voltage generating method for receiving a predetermined voltage and filtering the predetermined voltage to generate a reference voltage, the reference voltage generating method comprising:

utilizing a first capacitor to sample the predetermined voltage in a first stage;

coupling the first capacitor to a second capacitor in a second stage such that the first capacitor redistributes charges stored in the first capacitor with the second capacitor to generate the reference voltage; and

coupling a reference voltage sampling capacitor to the second capacitor in the first stage to obtain the reference voltage from the second capacitor.

20. The reference voltage generating method of claim 19 being utilized in a sigma-delta digital-to-analog converter (DAC).

21. The reference voltage generating method of claim 19 being utilized in a sigma-delta analog-to-digital converter (ADC).

22. The reference voltage generating method of claim 19, wherein the step of coupling the first capacitor to the second capacitor in the second stage to redistribute the charges stored in the first capacitor further comprises:

filtering out AC noises of the predetermined voltage.