Multilevel phase-change memory element and operating method

• US 7,254,059 B2
• Filed: 07/18/2005
• Issued: 08/07/2007
• Est. Priority Date: 10/08/2004
• Status: Expired due to Fees

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wang, Wen-Han, Shen, Kuei-Hung, Li, Chien-Ming
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): Sofocleous; Alexander
• Application Number:
  US11/182,783
• Publication Number:
  US 20060077706A1
• Time in Patent Office: 750 Days
• Field of Search: 365/161, 365/163, 365/185.03, 365/46, 365/148, 257/1, 257/2
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/008 Write by generating heat in the surroundings of the memory material, e.g. thermowrite
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/78 Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: H10N 70/043 by implantation
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A multilevel phase change memory element and operating method and electrodes, which are configured in a parallel structure to form a memory cell. A voltage-drive mode is employed to control and drive the memory element such that multilevel memory states may be achieved by imposing different voltage levels. The provided multilevel phase-change memory element has more bits and higher capacity than that of a memory element with a single phase-change layer.

Claims

1. A phase change memory element comprising:

a first phase change layer either in a crystalline state or in an amorphous state;

a second phase change layer either in a crystalline state or in an amorphous state;

a first top electrode and a second top electrode formed on one surface of the first phase change layer and the second phase change layer respectively, the first and second top electrodes being electrically connected in parallel for delivering electrical signals to change states of the first phase change layer and the second phase change layer; and

at least one bottom electrode connected to further surfaces of the first phase change layer and the second phase change layer respectively, the at least one bottom electrode being electrically connected to the first and second phase change layers in parallel and leading to a selecting component.

2. The memory element of claim 1, wherein materials of the first phase change layer and the second phase change layer are the same.

3. The memory element of claim 1, wherein materials of the first phase change layer and the second phase change layer are different.

4. The memory element of claim 1, wherein materials of the first top electrode and the second top electrode are the same.

5. The memory element of claim 1, wherein materials of the first top electrode and the second top electrode are different.

6. The memory element of claim 1, wherein a contact area of the first top electrode and the first phase change layer is the same as a contact area of the second top electrode and the second phase change layer.

7. The memory element of claim 1, wherein a contact area of the first top electrode and the first phase change layer is different from a contact area of the second top electrode and the second phase change layer.

8. The memory element of claim 1, wherein the at least one bottom electrode comprises a single electrode connected to the first phase change layer and the second phase change layer.

9. The memory element of claim 1, wherein the at least one bottom electrode comprises two electrodes connected to the first phase change layer and the second phase change layer respectively.

10. The memory element of claim 9, wherein materials of the two bottom electrodes are the same.

11. The memory element of claim 9, wherein materials of the two bottom electrodes are different.

12. The memory element of claim 1, further comprises a function layer between the first top electrode and the first phase change layer.

13. The memory element of claim 12, wherein the function layer comprises at least one of a heating layer for increasing heating efficiency, a nucleation accelerating layer for accelerating crystallization speed of the first phase change layer, and a diffusion stop layer for preventing diffusion between the first phase change layer and the first top electrode.

14. The memory element of claim 1, further comprises a function layer between the second top electrode and the first phase change layer.

15. The memory element of claim 12, wherein the function layer comprises at least one of a heating layer for increasing heating efficiency, a nucleation accelerating layer for accelerating crystallization speed of the second phase change layer, and a diffusion stop layer for preventing diffusion between the first phase change layer and the second top electrode.

16. A state transformation method for the phase change memory element of claim 1, comprising:

imposing a pulse to make both the first phase change layer and the second phase change layer amorphous showing a highest readout resistance;

imposing a pulse to make the first phase change layer amorphous and the second phase change layer crystalline showing a first intermediate readout resistance;

imposing a pulse to make the first phase change layer crystalline and the second phase change layer amorphous, showing a second intermediate readout resistance that is lower than the first intermediate resistance; and

imposing an electrical pulse to make both the first phase change layer and the second phase change layer crystalline showing a lowest readout resistance.

17. The state transformation method of claim 16, wherein the imposed pulse is a voltage pulse.

18. The memory element of claim 2, wherein the materials of the first phase change layer and the second phase change layer are doped eutectic SbTe composition.

19. The memory element of claim 2, wherein the materials of the first phase change layer and the second phase change layer are GeSbTe composition.

20. The memory element of claim 3, wherein the material of the first phase change layer is doped eutectic SbTe composition and the material of the second phase change layer is GeSbTe composition.

21. The memory element of claim 1, wherein the states include a first state when the first phase change layer and the second phase change layer are in the crystalline state, a second state when the first phase change layer is in the crystalline state and the second phase change layer is in the amorphous state, a third state when the first phase change layer is in the amorphous state and the second phase change layer is in the crystalline state, and a fourth state when the first phase change layer and the second phase change layer are in the amorphous state.

22. The memory element of claim 1, wherein the selecting component is a transistor.

23. A phase change memory element, comprising;

a first phase change layer that is either in a crystalline state or in an amorphous state, the first phase change layer having top and bottom ends;

a second phase change layer that is either in a crystalline state or in an amorphous state, the first phase change layer having top and bottom ends;

top means for permanently electrically connecting the top ends of the first and second phase change layers; and

bottom means for permanently electrically connecting the bottom ends of the first and second phase change layers.