Flash memory device having multi-level cell and reading and programming method thereof

• US 7,254,064 B2
• Filed: 02/17/2006
• Issued: 08/07/2007
• Est. Priority Date: 07/11/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Yeong-Taek, Kim, Dong-Hwan
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US11/356,620
• Publication Number:
  US 20060140002A1
• Time in Patent Office: 536 Days
• Field of Search: 365/189.05, 365/185.18, 365/185.19, 365/185.22, 365/185.24, 365/185.23
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output

Abstract

There is provided a flash memory device with multi-level cell and a reading and programming method thereof. The flash memory device with multi-level cell includes a memory cell array, a unit for precharging bit line, a bit line voltage supply circuit for supplying a voltage to the bit line, and first to third latch circuits each of which performs different function from each other. The reading and programming methods are performed by LSB and MSB reading and programming operations. A reading method in the memory device is achieved by reading an LSB two times and by reading an MSB one time. A programming method is achieved by programming an LSB one time and programming an MSB one time. Data having multi-levels can be programmed into memory cells by two times programming operations.

Claims

1. A NAND flash memory device comprising:

a memory cell array having a plurality of memory cells, each memory cell being connected to a word line and a bit line;

a word line voltage supply circuit for supplying a word line voltage to the word line;

a page buffer for supplying a bit line voltage to the bit line to program a selected memory cell or read data from the selected memory cell; and

a page buffer controller for supplying to the page buffer control signals for controlling the page buffer,

wherein during a LSB program operation, the page buffer supplies the bit line with a first bit line voltage for programming or a second bit line voltage for program inhibit in response to LSB data and the control signals;

wherein during a MSB program operation, the page buffer supplies the bit line with the second bit line voltage for program inhibit or the first and a third bit line voltage for programming in response to MSB data and the control signals; and

wherein the third bit line voltage is between the first bit line voltage and the second bit line voltage.

2. The NAND flash memory device of claim 1, wherein the first bit line voltage is a ground voltage, and the second bit line voltage is a power supply voltage.

3. The NAND flash memory device of claim 1, wherein the page buffer reads programmed LSB data from the selected memory cell prior to the MSB program operation, and then supplies one of the first to third bit line voltages to the bit line according to the read LSB data and the MSB data.

4. The NAND flash memory device of claim 3, wherein the page buffer comprises:

a precharge circuit for precharging the bit line prior to the respective LSB and MSB program operations;

a first latch circuit for latching the LSB data and MSB data to be respectively programmed to the selected memory cell;

a second latch circuit for latching the programmed LSB data being read from the selected memory cell; and

a bit line voltage supply circuit for supplying one of the first to third bit line voltages to the bit line according to data latched in the first and second latch circuits during the LSB and MSB program operations.

5. The NAND flash memory device of claim 4, wherein the page buffer further comprises a third latch circuit for receiving the LSB data and the MSB data from the external prior to the LSB and MSB program operations, and then dumping the received LSB and MSB data to the first latch circuit in response to the control signals.

6. The NAND flash memory device of claim 4, wherein the second latch circuit comprises:

a second latch for latching the programmed LSB data being read from the selected memory cell; and

a second reset circuit for resetting the second latch in response to the control signals.

7. The NAND flash memory device of claim 6, wherein the first latch circuit comprises:

a first latch for latching the LSB data and the MSB data to be programmed to the selected memory cell; and

a first reset circuit for resetting the first latch in response to the data of the second latch and the control signals.

8. The NAND flash memory device of claim 7, wherein the third latch circuit comprises:

a third latch for latching the received LSB data and the MSB data;

a third reset circuit for resetting the third latch in response to the control signals; and

a dump circuit for dumping the received LSB data and the MSB data in response to the control signals.

9. The NAND flash memory device of claim 4, wherein the bit line voltage supply circuit comprises:

a first voltage supply circuit for supplying the first bit line voltage in response to data latched in the first and second latch circuits;

a second voltage supply circuit for supplying the second bit line voltage in response to data latched to the first latch circuit; and

a third voltage supply circuit for supplying the third bit line voltage in response to the data latched to the first and second latch circuits.

10. The NAND flash memory device of claim 9, wherein the NAND flash memory device further comprises a voltage generator for generating the third bit line voltage.